From patchwork Sun Apr 3 22:25:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jeff Law X-Patchwork-Id: 52603 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 457BB385843E for ; Sun, 3 Apr 2022 22:25:58 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 457BB385843E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1649024758; bh=tTzFWjl37LQmYNXC7DCH9gj1WVWNQBX+3MgQTMJx6Yk=; h=Date:To:Subject:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=n6kdbn92QWcKiH2DK5MIVOwKUAFvKrqxrJW+Qmpx3GcRiu1BeKqnhyZdjLWuQLRXy qbFuN2NZihLw4iXECdJfBGPsn9TtBYFVatFBK++jMWdnho4GBd2EfvQlv6GEsTQfse wQLSaqJGXoaVnINHRiqj4o49HI/7LLQLrIwTJ37Q= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pf1-x42c.google.com (mail-pf1-x42c.google.com [IPv6:2607:f8b0:4864:20::42c]) by sourceware.org (Postfix) with ESMTPS id B77643858C53 for ; Sun, 3 Apr 2022 22:25:28 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org B77643858C53 Received: by mail-pf1-x42c.google.com with SMTP id z16so7315352pfh.3 for ; Sun, 03 Apr 2022 15:25:28 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:message-id:date:mime-version:user-agent :content-language:from:to:subject; bh=tTzFWjl37LQmYNXC7DCH9gj1WVWNQBX+3MgQTMJx6Yk=; b=vZ21WkcpyL6ninbKma2NznU09rn4rv4mRnpuX8lnyKnVrIsvTZl5pIAz+jNKJ3BIdD X6UkvpiEG/cFzRluJ7nDi/3YHzpCmI2GyPqa0lcGN9egbu1DmW9F4525XndN/4s+S3m9 jQek+NMGmenk6rFWAeAiiBhJo9BzMoeXgBJp9sFttFfyoNR1RCdrfR2kc7bBlpmIsGvQ tpnS6v9nIZE+Jnmjim3geo8VucVm4fg482ewyFKG4ctBRoZ5MNUtikwjuK0xHJbkYQr1 NwENJYa+NpC1vV4z7iVgiBXkkceS6oAjHvSdhxjMCDc2c252BIGHyUrT4k7ZfvqFnt0/ ibPA== X-Gm-Message-State: AOAM530ReNznM2m1wuOI07UPq0gwcmQDUOwVZaK3BTuwWusoDpJlmCdI F1MtZgX1FPuum5vgLDw8JcQSRpIcZIscrg== X-Google-Smtp-Source: ABdhPJwd/GsGANws1BOmA1DKIp1pv/VPMaENye9IJ3Ds/zhf+t8g+WFwjf5LwmX+FyPsHCuE8BHWvQ== X-Received: by 2002:a62:1dc9:0:b0:4fa:e4d2:7745 with SMTP id d192-20020a621dc9000000b004fae4d27745mr20910408pfd.61.1649024727131; Sun, 03 Apr 2022 15:25:27 -0700 (PDT) Received: from [172.31.0.204] (c-73-63-24-84.hsd1.ut.comcast.net. [73.63.24.84]) by smtp.gmail.com with ESMTPSA id d5-20020a633605000000b0039815688655sm8495496pga.0.2022.04.03.15.25.26 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 03 Apr 2022 15:25:26 -0700 (PDT) Message-ID: Date: Sun, 3 Apr 2022 16:25:25 -0600 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 Content-Language: en-US To: gcc-patches@gcc.gnu.org Subject: [committed][PR target/104987] Avoid "likely" forms of bbi[n] on iq2000. X-Spam-Status: No, score=-8.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Jeff Law via Gcc-patches From: Jeff Law Reply-To: Jeff Law Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" The iq2000 port is mis-compiling its mulsi3 libgcc2 function. AFAICT, the iq2000 has delay slots and can use "branch-likely" forms of conditional branches to annul-false the slot.   There's a support routine that handles creation of the  likely form.  However, that routine is not used by the bbi[n] instructions. If I manually add the likely extension to the bbi[b] instructions, the assembler complains  After a fair amount of digging it appears that the likely forms of bbi[n] are only supported on the IQ10 variant. Given this is a dead processor and has been so for a while it seems reasonable to just disallow annul-false slots for the bbi[n] instructions rather than try to handle them just for the IQ10 (which we don't have real support for anyway). This (of course) fixes the vrp13 regression.  But it also fixes nearly a thousand execution test failures in the testsuite (Yow!). Installed on the trunk, Jeff diff --git a/gcc/config/iq2000/iq2000.md b/gcc/config/iq2000/iq2000.md index fdb346f43ef..86361e27a86 100644 --- a/gcc/config/iq2000/iq2000.md +++ b/gcc/config/iq2000/iq2000.md @@ -165,6 +165,8 @@ (const_string "yes") (const_string "no")))) +;; Is this a bbi instruction or not +(define_attr "bbi" "no,yes" (const_string "no")) ;; Describe a user's asm statement. (define_asm_attributes @@ -183,11 +185,18 @@ (nil) (nil)]) -(define_delay (eq_attr "type" "branch") +;; GAS refuses to assemble bbi[n]l. So for bbi instructions, do not +;; allow them to annul-false. +(define_delay (and (eq_attr "type" "branch") (eq_attr "bbi" "no")) [(and (eq_attr "dslot" "ok_in_dslot") (eq_attr "length" "4")) (nil) (and (eq_attr "branch_likely" "yes") (and (eq_attr "dslot" "ok_in_dslot") (eq_attr "length" "4")))]) +(define_delay (and (eq_attr "type" "branch") (eq_attr "bbi" "yes")) + [(and (eq_attr "dslot" "ok_in_dslot") (eq_attr "length" "4")) + (nil) + (nil)]) + (define_delay (eq_attr "type" "call") [(and (eq_attr "dslot" "ok_in_dslot") (eq_attr "length" "4")) (nil) @@ -1114,7 +1123,8 @@ "" "bb%A2\\t%0(31-%1),%P2%P3" [(set_attr "length" "4") - (set_attr "type" "branch")]) + (set_attr "type" "branch") + (set_attr "bbi" "yes")]) (define_insn "" [(set (pc) @@ -1128,7 +1138,8 @@ "" "bb%A3\\t%0(31-%1),%P2%P3" [(set_attr "length" "4") - (set_attr "type" "branch")]) + (set_attr "type" "branch") + (set_attr "bbi" "yes")]) (define_insn "" [(set (pc) @@ -1142,7 +1153,8 @@ "0" "bb%A2\\t%0(31-%1),%P2%P3" [(set_attr "length" "4") - (set_attr "type" "branch")]) + (set_attr "type" "branch") + (set_attr "bbi" "yes")]) (define_insn "" [(set (pc) @@ -1156,7 +1168,8 @@ "0" "bb%A3\\t%0(31-%1),%P2%P3" [(set_attr "length" "4") - (set_attr "type" "branch")]) + (set_attr "type" "branch") + (set_attr "bbi" "yes")]) (define_insn "" [(set (pc) @@ -1169,7 +1182,8 @@ "" "bb%A3\\t%0(%p1),%P2%P3" [(set_attr "length" "4") - (set_attr "type" "branch")]) + (set_attr "type" "branch") + (set_attr "bbi" "yes")]) (define_insn "" [(set (pc) @@ -1182,7 +1196,8 @@ "" "bb%A2\\t%0(%p1),%P2%P3" [(set_attr "length" "4") - (set_attr "type" "branch")]) + (set_attr "type" "branch") + (set_attr "bbi" "yes")]) ;; ;; ....................