diff mbox series

[committed] Partial revert of recent changes

Message ID c55ba35f-8779-68f4-5e80-ddeb52e0b0e4@gmail.com
State Committed
Commit b9b7981f3d6919518372daf4c7e8c40dfc58f49d
Headers
Series [committed] Partial revert of recent changes |

Commit Message

Jeff Law May 6, 2023, 7:52 p.m. UTC 
  It turns out a couple of bits submitted by Michael had already been 
pushed to the trunk.  These two patches removes the duplicated bits.

Jeff
commit b9b7981f3d6919518372daf4c7e8c40dfc58f49d
Author: Jeff Law <jlaw@ventanamicro>
Date:   Sat May 6 11:36:37 2023 -0600

    Remove duplicated definition in risc-v vector support.
    
    gcc/
    
            * config/riscv/riscv-v.cc (autovec_use_vlmax_p): Remove
            duplicate definition.
commit 4c05f966a098744db9fa1e73074d7c08ace446fd
Author: Jeff Law <jlaw@ventanamicro>
Date:   Sat May 6 13:28:33 2023 -0600

    Delete duplicated riscv definition.
    
    gcc/
            * config/riscv/riscv-v.cc (riscv_vector_preferred_simd_mode): Delete.

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 9d699d455b0..8c7f3206771 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -190,44 +190,6 @@ autovec_use_vlmax_p (void)
 	  || riscv_autovec_preference == RVV_FIXED_VLMAX);
 }
 
-/* Return the vectorization machine mode for RVV according to LMUL.  */
-machine_mode
-riscv_vector_preferred_simd_mode (scalar_mode mode)
-{
-  /* We only enable auto-vectorization when TARGET_MIN_VLEN >= 128 &&
-     riscv_autovec_lmul < RVV_M2. Since GCC loop vectorizer report ICE
-     when we enable -march=rv64gc_zve32* and -march=rv32gc_zve64*.
-     in the 'can_duplicate_and_interleave_p' of tree-vect-slp.cc. Since we have
-     VNx1SImode in -march=*zve32* and VNx1DImode in -march=*zve64*, they are
-     enabled in targetm. vector_mode_supported_p and SLP vectorizer will try to
-     use them. Currently, we can support auto-vectorization in
-     -march=rv32_zve32x_zvl128b. Wheras, -march=rv32_zve32x_zvl32b or
-     -march=rv32_zve32x_zvl64b are disabled.  */
-  if (autovec_use_vlmax_p ())
-    {
-      /* If TARGET_MIN_VLEN < 128, we don't allow LMUL < 2
-	 auto-vectorization since Loop Vectorizer may use VNx1SImode or
-	 VNx1DImode to vectorize which will create ICE in the
-	 'can_duplicate_and_interleave_p' of tree-vect-slp.cc.  */
-      if (TARGET_MIN_VLEN < 128 && riscv_autovec_lmul < RVV_M2)
-	return word_mode;
-      /* We use LMUL = 1 as base bytesize which is BYTES_PER_RISCV_VECTOR and
-	 riscv_autovec_lmul as multiply factor to calculate the the NUNITS to
-	 get the auto-vectorization mode.  */
-      poly_uint64 nunits;
-      poly_uint64 vector_size
-	= BYTES_PER_RISCV_VECTOR * ((int) riscv_autovec_lmul);
-      poly_uint64 scalar_size = GET_MODE_SIZE (mode);
-      gcc_assert (multiple_p (vector_size, scalar_size, &nunits));
-      machine_mode rvv_mode;
-      if (get_vector_mode (mode, nunits).exists (&rvv_mode))
-	return rvv_mode;
-    }
-  /* TODO: We will support minimum length VLS auto-vectorization in the future.
-   */
-  return word_mode;
-}
-
 /* Emit an RVV unmask && vl mov from SRC to DEST.  */
 static void
 emit_pred_op (unsigned icode, rtx mask, rtx dest, rtx src, rtx len,
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 6f8b4abf46d..9d699d455b0 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -1015,17 +1015,6 @@  expand_tuple_move (machine_mode mask_mode, rtx *ops)
     }
 }
 
-/* SCALABLE means that the vector-length is agnostic (run-time invariant and
-   compile-time unknown). FIXED meands that the vector-length is specific
-   (compile-time known). Both RVV_SCALABLE and RVV_FIXED_VLMAX are doing
-   auto-vectorization using VLMAX vsetvl configuration.  */
-static bool
-autovec_use_vlmax_p (void)
-{
-  return riscv_autovec_preference == RVV_SCALABLE
-	 || riscv_autovec_preference == RVV_FIXED_VLMAX;
-}
-
 /* Return the vectorization machine mode for RVV according to LMUL.  */
 machine_mode
 preferred_simd_mode (scalar_mode mode)