diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 0100d67e9217..bf85baa53702 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -622,12 +622,6 @@ (define_mode_iterator SIGNBIT [(KF "FLOAT128_VECTOR_P (KFmode)")
 ; Iterator for ISA 3.0 supported floating point types
 (define_mode_iterator FP_ISA3 [SF DF])
 
-; SF/DF constraint for arithmetic on VSX registers using instructions added in
-; ISA 2.06 (power7).  This includes instructions that normally target DF mode,
-; but are used on SFmode, since internally SFmode values are kept in the DFmode
-; format.
-(define_mode_attr Fv		[(SF "wa") (DF "wa") (DI "wa")])
-
 ; Which isa is needed for those float instructions?
 (define_mode_attr Fisa		[(SF "p8v")  (DF "*") (DI "*")])
 
@@ -4868,8 +4862,8 @@ (define_expand "abs<mode>2"
   "")
 
 (define_insn "*abs<mode>2_fpr"
-  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<Fv>")
-	(abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "d,<Fv>")))]
+  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
+	(abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "d,wa")))]
   "TARGET_HARD_FLOAT"
   "@
    fabs %0,%1
@@ -4877,10 +4871,10 @@ (define_insn "*abs<mode>2_fpr"
   [(set_attr "type" "fpsimple")])
 
 (define_insn "*nabs<mode>2_fpr"
-  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<Fv>")
+  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
 	(neg:SFDF
 	 (abs:SFDF
-	  (match_operand:SFDF 1 "gpc_reg_operand" "d,<Fv>"))))]
+	  (match_operand:SFDF 1 "gpc_reg_operand" "d,wa"))))]
   "TARGET_HARD_FLOAT"
   "@
    fnabs %0,%1
@@ -4894,8 +4888,8 @@ (define_expand "neg<mode>2"
   "")
 
 (define_insn "*neg<mode>2_fpr"
-  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<Fv>")
-	(neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "d,<Fv>")))]
+  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
+	(neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "d,wa")))]
   "TARGET_HARD_FLOAT"
   "@
    fneg %0,%1
@@ -5274,9 +5268,9 @@ (define_expand "copysign<mode>3"
 ;; Use an unspec rather providing an if-then-else in RTL, to prevent the
 ;; compiler from optimizing -0.0
 (define_insn "copysign<mode>3_fcpsgn"
-  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<Fv>")
-	(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,<Fv>")
-		      (match_operand:SFDF 2 "gpc_reg_operand" "d,<Fv>")]
+  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
+	(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")
+		      (match_operand:SFDF 2 "gpc_reg_operand" "d,wa")]
 		     UNSPEC_COPYSIGN))]
   "TARGET_HARD_FLOAT && (TARGET_CMPB || VECTOR_UNIT_VSX_P (<MODE>mode))"
   "@
@@ -5308,9 +5302,9 @@ (define_expand "s<minmax><mode>3"
 })
 
 (define_insn "*s<minmax><mode>3_vsx"
-  [(set (match_operand:SFDF 0 "vsx_register_operand" "=<Fv>")
-	(fp_minmax:SFDF (match_operand:SFDF 1 "vsx_register_operand" "<Fv>")
-			(match_operand:SFDF 2 "vsx_register_operand" "<Fv>")))]
+  [(set (match_operand:SFDF 0 "vsx_register_operand" "=wa")
+	(fp_minmax:SFDF (match_operand:SFDF 1 "vsx_register_operand" "wa")
+			(match_operand:SFDF 2 "vsx_register_operand" "wa")))]
   "TARGET_VSX && TARGET_HARD_FLOAT"
 {
   return (TARGET_P9_MINMAX
@@ -5465,13 +5459,13 @@ (define_insn "*fsel<SFDF:mode><SFDF2:mode>4"
   [(set_attr "type" "fp")])
 
 (define_insn_and_split "*mov<SFDF:mode><SFDF2:mode>cc_p9"
-  [(set (match_operand:SFDF 0 "vsx_register_operand" "=&<SFDF:Fv>,<SFDF:Fv>")
+  [(set (match_operand:SFDF 0 "vsx_register_operand" "=&wa,wa")
 	(if_then_else:SFDF
 	 (match_operator:CCFP 1 "fpmask_comparison_operator"
-		[(match_operand:SFDF2 2 "vsx_register_operand" "<SFDF2:Fv>,<SFDF2:Fv>")
-		 (match_operand:SFDF2 3 "vsx_register_operand" "<SFDF2:Fv>,<SFDF2:Fv>")])
-	 (match_operand:SFDF 4 "vsx_register_operand" "<SFDF:Fv>,<SFDF:Fv>")
-	 (match_operand:SFDF 5 "vsx_register_operand" "<SFDF:Fv>,<SFDF:Fv>")))
+		[(match_operand:SFDF2 2 "vsx_register_operand" "wa,wa")
+		 (match_operand:SFDF2 3 "vsx_register_operand" "wa,wa")])
+	 (match_operand:SFDF 4 "vsx_register_operand" "wa,wa")
+	 (match_operand:SFDF 5 "vsx_register_operand" "wa,wa")))
    (clobber (match_scratch:V2DI 6 "=0,&wa"))]
   "TARGET_P9_MINMAX"
   "#"
@@ -5497,13 +5491,13 @@ (define_insn_and_split "*mov<SFDF:mode><SFDF2:mode>cc_p9"
 
 ;; Handle inverting the fpmask comparisons.
 (define_insn_and_split "*mov<SFDF:mode><SFDF2:mode>cc_invert_p9"
-  [(set (match_operand:SFDF 0 "vsx_register_operand" "=&<SFDF:Fv>,<SFDF:Fv>")
+  [(set (match_operand:SFDF 0 "vsx_register_operand" "=&wa,wa")
 	(if_then_else:SFDF
 	 (match_operator:CCFP 1 "invert_fpmask_comparison_operator"
-		[(match_operand:SFDF2 2 "vsx_register_operand" "<SFDF2:Fv>,<SFDF2:Fv>")
-		 (match_operand:SFDF2 3 "vsx_register_operand" "<SFDF2:Fv>,<SFDF2:Fv>")])
-	 (match_operand:SFDF 4 "vsx_register_operand" "<SFDF:Fv>,<SFDF:Fv>")
-	 (match_operand:SFDF 5 "vsx_register_operand" "<SFDF:Fv>,<SFDF:Fv>")))
+		[(match_operand:SFDF2 2 "vsx_register_operand" "wa,wa")
+		 (match_operand:SFDF2 3 "vsx_register_operand" "wa,wa")])
+	 (match_operand:SFDF 4 "vsx_register_operand" "wa,wa")
+	 (match_operand:SFDF 5 "vsx_register_operand" "wa,wa")))
    (clobber (match_scratch:V2DI 6 "=0,&wa"))]
   "TARGET_P9_MINMAX"
   "#"
@@ -5536,8 +5530,8 @@ (define_insn "*fpmask<mode>"
   [(set (match_operand:V2DI 0 "vsx_register_operand" "=wa")
 	(if_then_else:V2DI
 	 (match_operator:CCFP 1 "fpmask_comparison_operator"
-		[(match_operand:SFDF 2 "vsx_register_operand" "<Fv>")
-		 (match_operand:SFDF 3 "vsx_register_operand" "<Fv>")])
+		[(match_operand:SFDF 2 "vsx_register_operand" "wa")
+		 (match_operand:SFDF 3 "vsx_register_operand" "wa")])
 	 (match_operand:V2DI 4 "all_ones_constant" "")
 	 (match_operand:V2DI 5 "zero_constant" "")))]
   "TARGET_P9_MINMAX"
@@ -5545,11 +5539,11 @@ (define_insn "*fpmask<mode>"
   [(set_attr "type" "fpcompare")])
 
 (define_insn "*xxsel<mode>"
-  [(set (match_operand:SFDF 0 "vsx_register_operand" "=<Fv>")
+  [(set (match_operand:SFDF 0 "vsx_register_operand" "=wa")
 	(if_then_else:SFDF (ne (match_operand:V2DI 1 "vsx_register_operand" "wa")
 			       (match_operand:V2DI 2 "zero_constant" ""))
-			   (match_operand:SFDF 3 "vsx_register_operand" "<Fv>")
-			   (match_operand:SFDF 4 "vsx_register_operand" "<Fv>")))]
+			   (match_operand:SFDF 3 "vsx_register_operand" "wa")
+			   (match_operand:SFDF 4 "vsx_register_operand" "wa")))]
   "TARGET_P9_MINMAX"
   "xxsel %x0,%x4,%x3,%x1"
   [(set_attr "type" "vecmove")])
@@ -5684,7 +5678,7 @@ (define_insn "lfiwax"
 ; not be needed and also in case the insns are deleted as dead code.
 
 (define_insn_and_split "floatsi<mode>2_lfiwax"
-  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<Fv>")
+  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
 	(float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r,r")))
    (clobber (match_scratch:DI 2 "=d,wa"))]
   "TARGET_HARD_FLOAT && TARGET_LFIWAX
@@ -5723,7 +5717,7 @@ (define_insn_and_split "floatsi<mode>2_lfiwax"
    (set_attr "type" "fpload")])
 
 (define_insn_and_split "floatsi<mode>2_lfiwax_mem"
-  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<Fv>")
+  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
 	(float:SFDF
 	 (sign_extend:DI
 	  (match_operand:SI 1 "indexed_or_indirect_operand" "Z,Z"))))
@@ -5747,7 +5741,7 @@ (define_insn_and_split "floatsi<mode>2_lfiwax_mem"
    (set_attr "type" "fpload")])
 
 (define_insn_and_split "floatsi<SFDF:mode>2_lfiwax_<QHI:mode>_mem_zext"
-  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<Fv>")
+  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
 	(float:SFDF
 	 (zero_extend:SI
 	  (match_operand:QHI 1 "indexed_or_indirect_operand" "Z,Z"))))
@@ -5781,7 +5775,7 @@ (define_insn "lfiwzx"
    (set_attr "isa" "*,p8v,p8v,p9v")])
 
 (define_insn_and_split "floatunssi<mode>2_lfiwzx"
-  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<Fv>")
+  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
 	(unsigned_float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r,r")))
    (clobber (match_scratch:DI 2 "=d,wa"))]
   "TARGET_HARD_FLOAT && TARGET_LFIWZX && <SI_CONVERT_FP>"
@@ -5819,7 +5813,7 @@ (define_insn_and_split "floatunssi<mode>2_lfiwzx"
    (set_attr "type" "fpload")])
 
 (define_insn_and_split "floatunssi<mode>2_lfiwzx_mem"
-  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<Fv>")
+  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
 	(unsigned_float:SFDF
 	 (zero_extend:DI
 	  (match_operand:SI 1 "indexed_or_indirect_operand" "Z,Z"))))
@@ -6019,7 +6013,7 @@ (define_expand "float<QHI:mode><FP_ISA3:mode>2"
 })
 
 (define_insn_and_split "*float<QHI:mode><FP_ISA3:mode>2_internal"
-  [(set (match_operand:FP_ISA3 0 "vsx_register_operand" "=<Fv>,<Fv>,<Fv>")
+  [(set (match_operand:FP_ISA3 0 "vsx_register_operand" "=wa,wa,wa")
 	(float:FP_ISA3
 	 (match_operand:QHI 1 "reg_or_indexed_operand" "v,r,Z")))
    (clobber (match_scratch:DI 2 "=v,wa,v"))
@@ -6072,7 +6066,7 @@ (define_expand "floatuns<QHI:mode><FP_ISA3:mode>2"
 })
 
 (define_insn_and_split "*floatuns<QHI:mode><FP_ISA3:mode>2_internal"
-  [(set (match_operand:FP_ISA3 0 "vsx_register_operand" "=<Fv>,<Fv>,<Fv>")
+  [(set (match_operand:FP_ISA3 0 "vsx_register_operand" "=wa,wa,wa")
 	(unsigned_float:FP_ISA3
 	 (match_operand:QHI 1 "reg_or_indexed_operand" "v,r,Z")))
    (clobber (match_scratch:DI 2 "=v,wa,wa"))
@@ -6202,7 +6196,7 @@ (define_expand "fix_trunc<mode>di2"
 
 (define_insn "*fix_trunc<mode>di2_fctidz"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wa")
-	(fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d,<Fv>")))]
+	(fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d,wa")))]
   "TARGET_HARD_FLOAT && TARGET_FCFID"
   "@
    fctidz %0,%1
@@ -6321,7 +6315,7 @@ (define_insn_and_split "fixuns_trunc<mode>si2_stfiwx"
 
 (define_insn "fixuns_trunc<mode>di2"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wa")
-	(unsigned_fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d,<Fv>")))]
+	(unsigned_fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d,wa")))]
   "TARGET_HARD_FLOAT && TARGET_FCTIDUZ"
   "@
    fctiduz %0,%1
@@ -6471,7 +6465,7 @@ (define_expand "rs6000_set_fpscr_drn"
 (define_insn "fctiwz_<mode>"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wa")
 	(unspec:DI [(fix:SI
-		     (match_operand:SFDF 1 "gpc_reg_operand" "d,<Fv>"))]
+		     (match_operand:SFDF 1 "gpc_reg_operand" "d,wa"))]
 		   UNSPEC_FCTIWZ))]
   "TARGET_HARD_FLOAT"
   "@
@@ -6482,7 +6476,7 @@ (define_insn "fctiwz_<mode>"
 (define_insn "fctiwuz_<mode>"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wa")
 	(unspec:DI [(unsigned_fix:SI
-		     (match_operand:SFDF 1 "gpc_reg_operand" "d,<Fv>"))]
+		     (match_operand:SFDF 1 "gpc_reg_operand" "d,wa"))]
 		   UNSPEC_FCTIWUZ))]
   "TARGET_HARD_FLOAT && TARGET_FCTIWUZ"
   "@
@@ -6585,8 +6579,8 @@ (define_insn "lrint<mode>di2"
   [(set_attr "type" "fp")])
 
 (define_insn "btrunc<mode>2"
-  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<Fv>")
-	(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,<Fv>")]
+  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
+	(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")]
 		     UNSPEC_FRIZ))]
   "TARGET_HARD_FLOAT && TARGET_FPRND"
   "@
@@ -6595,8 +6589,8 @@ (define_insn "btrunc<mode>2"
   [(set_attr "type" "fp")])
 
 (define_insn "ceil<mode>2"
-  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<Fv>")
-	(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,<Fv>")]
+  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
+	(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")]
 		     UNSPEC_FRIP))]
   "TARGET_HARD_FLOAT && TARGET_FPRND"
   "@
@@ -6605,8 +6599,8 @@ (define_insn "ceil<mode>2"
   [(set_attr "type" "fp")])
 
 (define_insn "floor<mode>2"
-  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<Fv>")
-	(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,<Fv>")]
+  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
+	(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")]
 		     UNSPEC_FRIM))]
   "TARGET_HARD_FLOAT && TARGET_FPRND"
   "@
@@ -6624,8 +6618,8 @@ (define_insn "round<mode>2"
   [(set_attr "type" "fp")])
 
 (define_insn "*xsrdpi<mode>2"
-  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Fv>")
-	(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Fv>")]
+  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=wa")
+	(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "wa")]
 		     UNSPEC_XSRDPI))]
   "TARGET_HARD_FLOAT && TARGET_VSX"
   "xsrdpi %x0,%x1"
