From patchwork Sat Apr 22 16:47:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeff Law X-Patchwork-Id: 68166 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 669023858291 for ; Sat, 22 Apr 2023 16:47:36 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 669023858291 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1682182056; bh=qVseI3VvqyRs5sswCmuE1ZyTi1dNQ2bV3d6eBqjyXHw=; h=Date:To:Subject:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=M/tN/pzOHxs10CNbzpqCo626y0jhaAaE+8UYS6brwhI4cMpIFC4566foYELyXBK3v jSIYfNJosppYwvrfC0kOFmKc6uia/pRHXyTdbxJ+6DAKOzI/sj73Jx0izkucw+ToZz /hC5AdUQ+kA5W87FGulZo/QihB8//G/ZLajac9S4= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pl1-x62c.google.com (mail-pl1-x62c.google.com [IPv6:2607:f8b0:4864:20::62c]) by sourceware.org (Postfix) with ESMTPS id 3A5213858C83 for ; Sat, 22 Apr 2023 16:47:05 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 3A5213858C83 Received: by mail-pl1-x62c.google.com with SMTP id d9443c01a7336-1a667067275so26785405ad.1 for ; Sat, 22 Apr 2023 09:47:05 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682182022; x=1684774022; h=subject:to:from:content-language:user-agent:mime-version:date :message-id:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=qVseI3VvqyRs5sswCmuE1ZyTi1dNQ2bV3d6eBqjyXHw=; b=U77qwSDxIF/uMj3j+4tcLURxPisG6ij9n5hto+i1O8QlLaBLtZrNZmuCVYUz+Zfss/ SpKvSqCxRBXWlDn6ummKyu0bE7SpOaok9EWrC4d7lnaV5Q5uWQtOZy9zfqQhXUUJaTlj qJHbc8cku5t7IMMvVbvj1/1v6hZaXtnpKS4cRgjthDN3Vhqv0f3alZUlzFi4XC18XosP b0SUW2bcz+Jjr9z62WLbVBIuvJFTmsR9sqe0NKm6Kq/crQKjJ58oeXirf2sGga5DLiUB gHFjDgFyoIsQ7boKoA64u6wMdAs0/MnRLcFD4FmoT319JxdX+46kC5pT66NJJ+Gh/9MJ x4Uw== X-Gm-Message-State: AAQBX9fJxV2IWj0KRr4OeTIlZ+bFgOlb+JGHC34q4W/QJUetnHsoZqUI yClUzmLiIztSdW1yV7mTX6d8qqZ4qjw= X-Google-Smtp-Source: AKy350ZRhqYNDIlzvvmHqiTXc9DmoJEox7cufJHvDXX47CTnWIj47rSvxr6zp53byRf2aAgYFlX9SQ== X-Received: by 2002:a17:902:f68b:b0:1a6:48e6:ea7c with SMTP id l11-20020a170902f68b00b001a648e6ea7cmr10524522plg.6.1682182021876; Sat, 22 Apr 2023 09:47:01 -0700 (PDT) Received: from ?IPV6:2601:681:8600:13d0::99f? ([2601:681:8600:13d0::99f]) by smtp.gmail.com with ESMTPSA id x3-20020a170902ea8300b001a6aff2852dsm4218171plb.148.2023.04.22.09.47.00 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 22 Apr 2023 09:47:01 -0700 (PDT) Message-ID: Date: Sat, 22 Apr 2023 10:47:00 -0600 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.9.1 Content-Language: en-US To: "gcc-patches@gcc.gnu.org" Subject: [committed] Adjust rx movsicc tests X-Spam-Status: No, score=-8.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Jeff Law via Gcc-patches From: Jeff Law Reply-To: Jeff Law Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" The rx port has target specific test movsicc which is naturally meant to verify that if-conversion is happening on the expected cases. Unfortunately the test is poorly written. The core problem is there are 8 distinct tests and each of those tests is expected to generate a specific sequence. Unfortunately, various generic bits might turn an equality test into an inequality test or make other similar changes. The net result is the assembly matching patterns may find a particular sequence, but it may be for a different function than was originally intended. ie, test1's output may match the expected assembly for test5. Ugh! This patch breaks the movsicc test down into 8 distinct tests and adjusts the patterns they match. The nice thing is all these tests are supposed to have branches that use a bCC 1f form. So we can make them a bit more robust by ignoring the actual condition code used. So if we change eq to ne, as long as we match the movsicc pattern, we're OK. And the 1f style is only used by the movsicc pattern. With the tests broken down it's a lot easier to diagnose why one test fails after the recent changes to if-conversion. movsicc-3 fails because of the profitability test. It's more expensive than the other cases because of its use of (const_int 10) rather than (const_int 0). (const_int 0) naturally has a smaller cost. It looks to me like in this context (const_int 10) should have the same cost as (const_int 0). But I'm nowhere near well versed in the cost model for the rx port. So I'm just leaving the test as xfailed. If someone cares enough, they can dig into it further. Committed to the trunk, Jeff commit 00c49869fed445bf0f70cfa06b9bae1e75a393c8 Author: Jeff Law Date: Sat Apr 22 10:43:35 2023 -0600 Adjust rx movsicc tests The rx port has target specific test movsicc which is naturally meant to verify that if-conversion is happening on the expected cases. Unfortunately the test is poorly written. The core problem is there are 8 distinct tests and each of those tests is expected to generate a specific sequence. Unfortunately, various generic bits might turn an equality test into an inequality test or make other similar changes. The net result is the assembly matching patterns may find a particular sequence, but it may be for a different function than was originally intended. ie, test1's output may match the expected assembly for test5. Ugh! This patch breaks the movsicc test down into 8 distinct tests and adjusts the patterns they match. The nice thing is all these tests are supposed to have branches that use a bCC 1f form. So we can make them a bit more robust by ignoring the actual condition code used. So if we change eq to ne, as long as we match the movsicc pattern, we're OK. And the 1f style is only used by the movsicc pattern. With the tests broken down it's a lot easier to diagnose why one test fails after the recent changes to if-conversion. movsicc-3 fails because of the profitability test. It's more expensive than the other cases because of its use of (const_int 10) rather than (const_int 0). (const_int 0) naturally has a smaller cost. It looks to me like in this context (const_int 10) should have the same cost as (const_int 0). But I'm nowhere near well versed in the cost model for the rx port. So I'm just leaving the test as xfailed. If someone cares enough, they can dig into it further. gcc/testsuite * gcc.target/rx/movsicc.c: Broken down into ... * gcc.target/rx/movsicc-1.c: Here. * gcc.target/rx/movsicc-2.c: Here. * gcc.target/rx/movsicc-3.c: Here. xfail one test. * gcc.target/rx/movsicc-4.c: Here. * gcc.target/rx/movsicc-5.c: Here. * gcc.target/rx/movsicc-6.c: Here. * gcc.target/rx/movsicc-7.c: Here. * gcc.target/rx/movsicc-8.c: Here. diff --git a/gcc/testsuite/gcc.target/rx/movsicc-1.c b/gcc/testsuite/gcc.target/rx/movsicc-1.c new file mode 100644 index 00000000000..09234ea0642 --- /dev/null +++ b/gcc/testsuite/gcc.target/rx/movsicc-1.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-Os" } */ + +typedef unsigned char u8; +typedef unsigned short u16; +signed int Xa, Xb; + +signed int stzreg_beq(int i, int a, int b) +{ + signed int x; + x = a; + if (i) + x = b; + return x; +} + +/* { dg-final { scan-assembler "b.. 1f" } } */ + diff --git a/gcc/testsuite/gcc.target/rx/movsicc-2.c b/gcc/testsuite/gcc.target/rx/movsicc-2.c new file mode 100644 index 00000000000..7d730c4e6b3 --- /dev/null +++ b/gcc/testsuite/gcc.target/rx/movsicc-2.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-Os" } */ + +typedef unsigned char u8; +typedef unsigned short u16; +signed int Xa, Xb; + +signed int stzreg_bge(int i, int a, int b, int c) +{ + signed int x; + x = a; + if (i0) + x = b; + return x; +} + +/* { dg-final { scan-assembler "b.. 1f" } } */ + diff --git a/gcc/testsuite/gcc.target/rx/movsicc-5.c b/gcc/testsuite/gcc.target/rx/movsicc-5.c new file mode 100644 index 00000000000..0febb6800b6 --- /dev/null +++ b/gcc/testsuite/gcc.target/rx/movsicc-5.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-Os" } */ + +typedef unsigned char u8; +typedef unsigned short u16; +signed int Xa, Xb; + +signed int stzreg_blt(int i, int a, int b) +{ + signed int x; + x = a; + if (i<0) + x = b; + return x; +} + +/* { dg-final { scan-assembler "b.. 1f" } } */ + diff --git a/gcc/testsuite/gcc.target/rx/movsicc-6.c b/gcc/testsuite/gcc.target/rx/movsicc-6.c new file mode 100644 index 00000000000..69f312e6df4 --- /dev/null +++ b/gcc/testsuite/gcc.target/rx/movsicc-6.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-Os" } */ + +typedef unsigned char u8; +typedef unsigned short u16; +signed int Xa, Xb; + +signed int stzreg_bne(int i, int a, int b) +{ + signed int x; + x = a; + if (!i) + x = b; + return x; +} + +/* { dg-final { scan-assembler "b.. 1f" } } */ + diff --git a/gcc/testsuite/gcc.target/rx/movsicc-7.c b/gcc/testsuite/gcc.target/rx/movsicc-7.c new file mode 100644 index 00000000000..a1a22e2f16b --- /dev/null +++ b/gcc/testsuite/gcc.target/rx/movsicc-7.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-Os" } */ + +typedef unsigned char u8; +typedef unsigned short u16; +signed int Xa, Xb; + +signed int stzimm_le( int i, int a ) +{ + signed int x; + x = a; + if (i>0) + x = 5; + return x; +} + +/* { dg-final { scan-assembler "b.. 1f" } } */ diff --git a/gcc/testsuite/gcc.target/rx/movsicc-8.c b/gcc/testsuite/gcc.target/rx/movsicc-8.c new file mode 100644 index 00000000000..be59e643913 --- /dev/null +++ b/gcc/testsuite/gcc.target/rx/movsicc-8.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-Os" } */ + +typedef unsigned char u8; +typedef unsigned short u16; +signed int Xa, Xb; + +signed int stzimm_le_r( int i, int a ) +{ + signed int x; + x = a; + if (i<0) + x = 5; + return x; +} + +/* { dg-final { scan-assembler "b.. 1f" } } */ diff --git a/gcc/testsuite/gcc.target/rx/movsicc.c b/gcc/testsuite/gcc.target/rx/movsicc.c deleted file mode 100644 index d8e6bcc3055..00000000000 --- a/gcc/testsuite/gcc.target/rx/movsicc.c +++ /dev/null @@ -1,94 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-Os" } */ - -typedef unsigned char u8; -typedef unsigned short u16; -signed int Xa, Xb; - -signed int stzreg_beq(int i, int a, int b) -{ - signed int x; - x = a; - if (i) - x = b; - return x; -} - -/* { dg-final { scan-assembler "bne 1f" } } */ - -signed int stzreg_bge(int i, int a, int b, int c) -{ - signed int x; - x = a; - if (i0) - x = b; - return x; -} - -/* { dg-final { scan-assembler "bgt 1f" } } */ - -signed int stzreg_blt(int i, int a, int b) -{ - signed int x; - x = a; - if (i<0) - x = b; - return x; -} - -/* { dg-final { scan-assembler "blt 1f" } } */ - -signed int stzreg_bne(int i, int a, int b) -{ - signed int x; - x = a; - if (!i) - x = b; - return x; -} - -/* { dg-final { scan-assembler "beq 1f" } } */ - -signed int stzimm_le( int i, int a ) -{ - signed int x; - x = a; - if (i>0) - x = 5; - return x; -} - -/* { dg-final { scan-assembler "ble 1f" } } */ - -signed int stzimm_le_r( int i, int a ) -{ - signed int x; - x = a; - if (i<0) - x = 5; - return x; -} - -/* { dg-final { scan-assembler "bge 1f" } } */