[committed] Adjust rx movsicc tests

Message ID bd9fe99b-65ff-4d26-ae3e-5a9668831344@gmail.com
State Committed
Commit 00c49869fed445bf0f70cfa06b9bae1e75a393c8
Headers
Series [committed] Adjust rx movsicc tests |

Commit Message

Jeff Law April 22, 2023, 4:47 p.m. UTC
  The rx port has target specific test movsicc which is naturally meant to 
verify that if-conversion is happening on the expected cases.

Unfortunately the test is poorly written.  The core problem is there are 
8 distinct tests and each of those tests is expected to generate a 
specific sequence.  Unfortunately, various generic bits might turn an 
equality test into an inequality test or make other similar changes.

The net result is the assembly matching patterns may find a particular 
sequence, but it may be for a different function than was originally 
intended.  ie, test1's output may match the expected assembly for test5. 
  Ugh!

This patch breaks the movsicc test down into 8 distinct tests and 
adjusts the patterns they match.  The nice thing is all these tests are 
supposed to have branches that use a bCC 1f form.  So we can make them a 
bit more robust by ignoring the actual condition code used.  So if we 
change eq to ne, as long as we match the movsicc pattern, we're OK.  And 
the 1f style is only used by the movsicc pattern.

With the tests broken down it's a lot easier to diagnose why one test 
fails after the recent changes to if-conversion.  movsicc-3 fails 
because of the profitability test.  It's more expensive than the other 
cases because of its use of (const_int 10) rather than (const_int 0). 
(const_int 0) naturally has a smaller cost.

It looks to me like in this context (const_int 10) should have the same 
cost as (const_int 0).  But I'm nowhere near well versed in the cost 
model for the rx port.  So I'm just leaving the test as xfailed.  If 
someone cares enough, they can dig into it further.



Committed to the trunk,

Jeff
commit 00c49869fed445bf0f70cfa06b9bae1e75a393c8
Author: Jeff Law <jlaw@ventanamicro>
Date:   Sat Apr 22 10:43:35 2023 -0600

    Adjust rx movsicc tests
    
    The rx port has target specific test movsicc which is naturally meant to verify
    that if-conversion is happening on the expected cases.
    
    Unfortunately the test is poorly written.  The core problem is there are 8
    distinct tests and each of those tests is expected to generate a specific
    sequence.  Unfortunately, various generic bits might turn an equality test
    into an inequality test or make other similar changes.
    
    The net result is the assembly matching patterns may find a particular sequence,
    but it may be for a different function than was originally intended.  ie,
    test1's output may match the expected assembly for test5.  Ugh!
    
    This patch breaks the movsicc test down into 8 distinct tests and adjusts the
    patterns they match.  The nice thing is all these tests are supposed to have
    branches that use a bCC 1f form.  So we can make them a bit more robust by
    ignoring the actual condition code used.  So if we change eq to ne, as long
    as we match the movsicc pattern, we're OK.  And the 1f style is only used by
    the movsicc pattern.
    
    With the tests broken down it's a lot easier to diagnose why one test fails
    after the recent changes to if-conversion.  movsicc-3 fails because of the
    profitability test.  It's more expensive than the other cases because of its
    use of (const_int 10) rather than (const_int 0).  (const_int 0) naturally has
    a smaller cost.
    
    It looks to me like in this context (const_int 10) should have the same cost
     as (const_int 0).  But I'm nowhere near well versed in the cost model for the
    rx port.  So I'm just leaving the test as xfailed.  If someone cares enough,
    they can dig into it further.
    
    gcc/testsuite
            * gcc.target/rx/movsicc.c: Broken down into ...
            * gcc.target/rx/movsicc-1.c: Here.
            * gcc.target/rx/movsicc-2.c: Here.
            * gcc.target/rx/movsicc-3.c: Here.  xfail one test.
            * gcc.target/rx/movsicc-4.c: Here.
            * gcc.target/rx/movsicc-5.c: Here.
            * gcc.target/rx/movsicc-6.c: Here.
            * gcc.target/rx/movsicc-7.c: Here.
            * gcc.target/rx/movsicc-8.c: Here.
  

Patch

diff --git a/gcc/testsuite/gcc.target/rx/movsicc-1.c b/gcc/testsuite/gcc.target/rx/movsicc-1.c
new file mode 100644
index 00000000000..09234ea0642
--- /dev/null
+++ b/gcc/testsuite/gcc.target/rx/movsicc-1.c
@@ -0,0 +1,18 @@ 
+/* { dg-do compile } */
+/* { dg-options "-Os" } */
+
+typedef unsigned char u8;
+typedef unsigned short u16;
+signed int Xa, Xb;
+
+signed int stzreg_beq(int i, int a, int b)
+{
+  signed int x;
+  x = a;
+  if (i)
+    x = b;
+  return x;
+}
+
+/* { dg-final { scan-assembler "b.. 1f" } } */
+
diff --git a/gcc/testsuite/gcc.target/rx/movsicc-2.c b/gcc/testsuite/gcc.target/rx/movsicc-2.c
new file mode 100644
index 00000000000..7d730c4e6b3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/rx/movsicc-2.c
@@ -0,0 +1,18 @@ 
+/* { dg-do compile } */
+/* { dg-options "-Os" } */
+
+typedef unsigned char u8;
+typedef unsigned short u16;
+signed int Xa, Xb;
+
+signed int stzreg_bge(int i, int a, int b, int c)
+{
+  signed int x;
+  x = a;
+  if (i<c)
+    x = b;
+  return x;
+}
+
+/* { dg-final { scan-assembler "b.. 1f" } } */
+
diff --git a/gcc/testsuite/gcc.target/rx/movsicc-3.c b/gcc/testsuite/gcc.target/rx/movsicc-3.c
new file mode 100644
index 00000000000..84a56e2e30b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/rx/movsicc-3.c
@@ -0,0 +1,18 @@ 
+/* { dg-do compile } */
+/* { dg-options "-Os" } */
+
+typedef unsigned char u8;
+typedef unsigned short u16;
+signed int Xa, Xb;
+
+signed int stzreg_bgt(int i, int a, int b)
+{
+  signed int x;
+  x = a;
+  if (i<10)
+    x = b;
+  return x;
+}
+
+/* { dg-final { scan-assembler "b.. 1f" } } */
+
diff --git a/gcc/testsuite/gcc.target/rx/movsicc-4.c b/gcc/testsuite/gcc.target/rx/movsicc-4.c
new file mode 100644
index 00000000000..fef30cfe5e8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/rx/movsicc-4.c
@@ -0,0 +1,18 @@ 
+/* { dg-do compile } */
+/* { dg-options "-Os" } */
+
+typedef unsigned char u8;
+typedef unsigned short u16;
+signed int Xa, Xb;
+
+signed int stzreg_ble(int i, int a, int b)
+{
+  signed int x;
+  x = a;
+  if (i>0)
+    x = b;
+  return x;
+}
+
+/* { dg-final { scan-assembler "b.. 1f" } } */
+
diff --git a/gcc/testsuite/gcc.target/rx/movsicc-5.c b/gcc/testsuite/gcc.target/rx/movsicc-5.c
new file mode 100644
index 00000000000..0febb6800b6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/rx/movsicc-5.c
@@ -0,0 +1,18 @@ 
+/* { dg-do compile } */
+/* { dg-options "-Os" } */
+
+typedef unsigned char u8;
+typedef unsigned short u16;
+signed int Xa, Xb;
+
+signed int stzreg_blt(int i, int a, int b)
+{
+  signed int x;
+  x = a;
+  if (i<0)
+    x = b;
+  return x;
+}
+
+/* { dg-final { scan-assembler "b.. 1f" } } */
+
diff --git a/gcc/testsuite/gcc.target/rx/movsicc-6.c b/gcc/testsuite/gcc.target/rx/movsicc-6.c
new file mode 100644
index 00000000000..69f312e6df4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/rx/movsicc-6.c
@@ -0,0 +1,18 @@ 
+/* { dg-do compile } */
+/* { dg-options "-Os" } */
+
+typedef unsigned char u8;
+typedef unsigned short u16;
+signed int Xa, Xb;
+
+signed int stzreg_bne(int i, int a, int b)
+{
+  signed int x;
+  x = a;
+  if (!i)
+    x = b;
+  return x;
+}
+
+/* { dg-final { scan-assembler "b.. 1f" } } */
+
diff --git a/gcc/testsuite/gcc.target/rx/movsicc-7.c b/gcc/testsuite/gcc.target/rx/movsicc-7.c
new file mode 100644
index 00000000000..a1a22e2f16b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/rx/movsicc-7.c
@@ -0,0 +1,17 @@ 
+/* { dg-do compile } */
+/* { dg-options "-Os" } */
+
+typedef unsigned char u8;
+typedef unsigned short u16;
+signed int Xa, Xb;
+
+signed int stzimm_le( int i, int a )
+{
+  signed int x;
+  x = a;
+  if (i>0)
+    x = 5;
+  return x;
+}
+
+/* { dg-final { scan-assembler "b.. 1f" } } */
diff --git a/gcc/testsuite/gcc.target/rx/movsicc-8.c b/gcc/testsuite/gcc.target/rx/movsicc-8.c
new file mode 100644
index 00000000000..be59e643913
--- /dev/null
+++ b/gcc/testsuite/gcc.target/rx/movsicc-8.c
@@ -0,0 +1,17 @@ 
+/* { dg-do compile } */
+/* { dg-options "-Os" } */
+
+typedef unsigned char u8;
+typedef unsigned short u16;
+signed int Xa, Xb;
+
+signed int stzimm_le_r( int i, int a )
+{
+  signed int x;
+  x = a;
+  if (i<0)
+    x = 5;
+  return x;
+}
+
+/* { dg-final { scan-assembler "b.. 1f" } } */
diff --git a/gcc/testsuite/gcc.target/rx/movsicc.c b/gcc/testsuite/gcc.target/rx/movsicc.c
deleted file mode 100644
index d8e6bcc3055..00000000000
--- a/gcc/testsuite/gcc.target/rx/movsicc.c
+++ /dev/null
@@ -1,94 +0,0 @@ 
-/* { dg-do compile } */
-/* { dg-options "-Os" } */
-
-typedef unsigned char u8;
-typedef unsigned short u16;
-signed int Xa, Xb;
-
-signed int stzreg_beq(int i, int a, int b)
-{
-  signed int x;
-  x = a;
-  if (i)
-    x = b;
-  return x;
-}
-
-/* { dg-final { scan-assembler "bne 1f" } } */
-
-signed int stzreg_bge(int i, int a, int b, int c)
-{
-  signed int x;
-  x = a;
-  if (i<c)
-    x = b;
-  return x;
-}
-
-/* { dg-final { scan-assembler "blt 1f" } } */
-
-signed int stzreg_bgt(int i, int a, int b)
-{
-  signed int x;
-  x = a;
-  if (i<10)
-    x = b;
-  return x;
-}
-
-/* { dg-final { scan-assembler "ble 1f" } } */
-
-signed int stzreg_ble(int i, int a, int b)
-{
-  signed int x;
-  x = a;
-  if (i>0)
-    x = b;
-  return x;
-}
-
-/* { dg-final { scan-assembler "bgt 1f" } } */
-
-signed int stzreg_blt(int i, int a, int b)
-{
-  signed int x;
-  x = a;
-  if (i<0)
-    x = b;
-  return x;
-}
-
-/* { dg-final { scan-assembler "blt 1f" } } */
-
-signed int stzreg_bne(int i, int a, int b)
-{
-  signed int x;
-  x = a;
-  if (!i)
-    x = b;
-  return x;
-}
-
-/* { dg-final { scan-assembler "beq 1f" } } */
-
-signed int stzimm_le( int i, int a )
-{
-  signed int x;
-  x = a;
-  if (i>0)
-    x = 5;
-  return x;
-}
-
-/* { dg-final { scan-assembler "ble 1f" } } */
-
-signed int stzimm_le_r( int i, int a )
-{
-  signed int x;
-  x = a;
-  if (i<0)
-    x = 5;
-  return x;
-}
-
-/* { dg-final { scan-assembler "bge 1f" } } */