diff --git a/gcc/config.gcc b/gcc/config.gcc
index 498c51e619d..58e38f70aa6 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -448,6 +448,7 @@ microblaze*-*-*)
         ;;
 mips*-*-*)
 	cpu_type=mips
+	md_file=mips/mips-classic.md
 	d_target_objs="mips-d.o"
 	extra_headers="loongson.h loongson-mmiintrin.h msa.h"
 	extra_objs="frame-header-opt.o"
diff --git a/gcc/config/mips/mips-classic.md b/gcc/config/mips/mips-classic.md
new file mode 100644
index 00000000000..0f7efc4d5d8
--- /dev/null
+++ b/gcc/config/mips/mips-classic.md
@@ -0,0 +1,142 @@
+;;  Mips.md	     Machine Description for MIPS based processors
+;;  Copyright (C) 1989-2021 Free Software Foundation, Inc.
+;;  Contributed by   A. Lichnewsky, lich@inria.inria.fr
+;;  Changes by       Michael Meissner, meissner@osf.org
+;;  64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
+;;  Brendan Eich, brendan@microunity.com.
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
+
+(define_enum "processor" [
+  r3000
+  4kc
+  4kp
+  5kc
+  5kf
+  20kc
+  24kc
+  24kf2_1
+  24kf1_1
+  74kc
+  74kf2_1
+  74kf1_1
+  74kf3_2
+  loongson_2e
+  loongson_2f
+  gs464
+  gs464e
+  gs264e
+  m4k
+  octeon
+  octeon2
+  octeon3
+  r3900
+  r6000
+  r4000
+  r4100
+  r4111
+  r4120
+  r4130
+  r4300
+  r4600
+  r4650
+  r4700
+  r5000
+  r5400
+  r5500
+  r5900
+  r7000
+  r8000
+  r9000
+  r10000
+  sb1
+  sb1a
+  sr71000
+  xlr
+  xlp
+  p5600
+  m5100
+  i6400
+  p6600
+])
+
+(include "mips.md")
+
+(include "i6400.md")
+(include "p5600.md")
+(include "m5100.md")
+(include "p6600.md")
+(include "4k.md")
+(include "5k.md")
+(include "20kc.md")
+(include "24k.md")
+(include "74k.md")
+(include "3000.md")
+(include "4000.md")
+(include "4100.md")
+(include "4130.md")
+(include "4300.md")
+(include "4600.md")
+(include "5000.md")
+(include "5400.md")
+(include "5500.md")
+(include "6000.md")
+(include "7000.md")
+(include "9000.md")
+(include "10000.md")
+(include "loongson2ef.md")
+(include "gs464.md")
+(include "gs464e.md")
+(include "gs264e.md")
+(include "octeon.md")
+(include "sb1.md")
+(include "sr71k.md")
+(include "xlr.md")
+(include "xlp.md")
+(include "generic.md")
+
+;; Synchronization instructions.
+
+(include "sync.md")
+
+; The MIPS Paired-Single Floating Point and MIPS-3D Instructions.
+
+(include "mips-ps-3d.md")
+
+; The MIPS DSP Instructions.
+
+(include "mips-dsp.md")
+
+; The MIPS DSP REV 2 Instructions.
+
+(include "mips-dspr2.md")
+
+; MIPS fixed-point instructions.
+(include "mips-fixed.md")
+
+; microMIPS patterns.
+(include "micromips.md")
+
+; Loongson MultiMedia extensions Instructions (MMI) patterns.
+(include "loongson-mmi.md")
+
+; The MIPS MSA Instructions.
+(include "mips-msa.md")
+
+(define_c_enum "unspec" [
+  UNSPEC_ADDRESS_FIRST
+])
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index ab63575eb26..8f125a4ddec 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -234,12 +234,14 @@ enum mips_builtin_type {
      value and the arguments are mapped to operands 0 and above.  */
   MIPS_BUILTIN_DIRECT_NO_TARGET,
 
+#ifdef MIPS_SUPPORT_PS_3D
   /* The function corresponds to a comparison instruction followed by
      a mips_cond_move_tf_ps pattern.  The first two arguments are the
      values to compare and the second two arguments are the vector
      operands for the movt.ps or movf.ps instruction (in assembly order).  */
   MIPS_BUILTIN_MOVF,
   MIPS_BUILTIN_MOVT,
+#endif
 
   /* The function corresponds to a V2SF comparison instruction.  Operand 0
      of this instruction is the result of the comparison, which has mode
@@ -263,8 +265,10 @@ enum mips_builtin_type {
      combined with a compare instruction.  */
   MIPS_BUILTIN_MSA_TEST_BRANCH,
 
+#ifdef MIPS_SUPPORT_DSP
   /* For generating bposge32 branch instructions in MIPS32 DSP ASE.  */
   MIPS_BUILTIN_BPOSGE32
+#endif
 };
 
 /* Invoke MACRO (COND) for each C.cond.fmt condition.  */
@@ -4797,9 +4801,11 @@ mips_split_move_p (rtx dest, rtx src, enum mips_split_type split_type)
 	return false;
     }
 
+#ifdef MIPS_SUPPORT_MSA
   /* Check if MSA moves need splitting.  */
   if (MSA_SUPPORTED_MODE_P (GET_MODE (dest)))
     return mips_split_128bit_move_p (dest, src);
+#endif
 
   /* Otherwise split all multiword moves.  */
   return size > UNITS_PER_WORD;
@@ -4815,9 +4821,13 @@ mips_split_move (rtx dest, rtx src, enum mips_split_type split_type, rtx insn_)
   rtx low_dest;
 
   gcc_checking_assert (mips_split_move_p (dest, src, split_type));
+#ifdef MIPS_SUPPORT_MSA
   if (MSA_SUPPORTED_MODE_P (GET_MODE (dest)))
     mips_split_128bit_move (dest, src);
   else if (FP_REG_RTX_P (dest) || FP_REG_RTX_P (src))
+#else
+  if (FP_REG_RTX_P (dest) || FP_REG_RTX_P (src))
+#endif
     {
       if (!TARGET_64BIT && GET_MODE (dest) == DImode)
 	emit_insn (gen_move_doubleword_fprdi (dest, src));
@@ -4916,6 +4926,7 @@ mips_insn_split_type (rtx insn)
   return SPLIT_IF_NECESSARY;
 }
 
+#ifdef MIPS_SUPPORT_MSA
 /* Return true if a 128-bit move from SRC to DEST should be split.  */
 
 bool
@@ -5108,6 +5119,7 @@ mips_split_msa_fill_d (rtx dest, rtx src)
   emit_insn (gen_msa_insert_w (new_dest, high, new_dest, GEN_INT (1 << 1)));
   emit_insn (gen_msa_insert_w (new_dest, high, new_dest, GEN_INT (1 << 3)));
 }
+#endif
 
 /* Return true if a move from SRC to DEST in INSN should be split.  */
 
@@ -5639,6 +5651,7 @@ mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
 	  *op1 = const0_rtx;
 	}
     }
+#ifdef MIPS_SUPPORT_DSP
   else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_op0)))
     {
       *op0 = gen_rtx_REG (CCDSPmode, CCDSP_CC_REGNUM);
@@ -5646,6 +5659,7 @@ mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
       *code = NE;
       *op1 = const0_rtx;
     }
+#endif
   else
     {
       enum rtx_code cmp_code;
@@ -5728,6 +5742,7 @@ mips_expand_conditional_branch (rtx *operands)
   emit_jump_insn (gen_condjump (condition, operands[3]));
 }
 
+#ifdef MIPS_SUPPORT_PS_3D
 /* Implement:
 
    (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
@@ -5751,6 +5766,7 @@ mips_expand_vcondv2sf (rtx dest, rtx true_src, rtx false_src,
     emit_insn (gen_mips_cond_move_tf_ps (dest, true_src, false_src,
 					 cmp_result));
 }
+#endif
 
 /* Perform the comparison in OPERANDS[1].  Move OPERANDS[2] into OPERANDS[0]
    if the condition holds, otherwise move OPERANDS[3] into OPERANDS[0].  */
@@ -9589,6 +9605,7 @@ mips_dwarf_frame_reg_mode (int regno)
   return mode;
 }
 
+#ifdef MIPS_SUPPORT_DSP
 /* DSP ALU can bypass data with no delays for the following pairs. */
 enum insn_code dspalu_bypass_table[][2] =
 {
@@ -9619,6 +9636,8 @@ mips_dspalu_bypass_p (rtx out_insn, rtx in_insn)
 
   return false;
 }
+#endif
+
 /* Implement ASM_OUTPUT_ASCII.  */
 
 void
@@ -11203,6 +11222,7 @@ mips_compute_frame_info (void)
       frame->cop0_sp_offset = offset - UNITS_PER_WORD;
     }
 
+#ifdef MIPS_SUPPORT_FRAME_HEADER_OPT
   /* Determine if we can save the callee-saved registers in the frame
      header.  Restrict this to functions where there is no other reason
      to allocate stack space so that we can eliminate the instructions
@@ -11231,6 +11251,7 @@ mips_compute_frame_info (void)
       frame->gp_sp_offset = REG_PARM_STACK_SPACE(cfun) - UNITS_PER_WORD;
       cfun->machine->use_frame_header_for_callee_saved_regs = true;
     }
+#endif
 
   /* Move above the callee-allocated varargs save area.  */
   offset += MIPS_STACK_ALIGN (cfun->machine->varargs_size);
@@ -12783,8 +12804,10 @@ mips_expand_epilogue (bool sibcall_p)
 	      rtx reg = gen_rtx_REG (Pmode, GP_REG_FIRST + 7);
 	      pat = gen_return_internal (reg);
 	    }
+#ifdef MIPS_SUPPORT_MICROMIPS
 	  else if (use_jraddiusp_p)
 	    pat = gen_jraddiusp (GEN_INT (step2));
+#endif
 	  else
 	    {
 	      rtx reg = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM);
@@ -14640,7 +14663,7 @@ mips_store_data_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn)
   return store_data_bypass_p (out_insn, in_insn);
 }
 
-
+#ifdef MIPS_SUPPORT_LOONGSON
 /* Variables and flags used in scheduler hooks when tuning for
    Loongson 2E/2F.  */
 static struct
@@ -14674,6 +14697,7 @@ static struct
   rtx_insn *falu1_turn_enabled_insn;
   rtx_insn *falu2_turn_enabled_insn;
 } mips_ls2;
+#endif
 
 /* Implement TARGET_SCHED_ADJUST_COST.  We assume that anti and output
    dependencies have no cost, except on the 20Kc where output-dependence
@@ -14746,6 +14770,7 @@ mips_issue_rate (void)
     }
 }
 
+#ifdef MIPS_SUPPORT_LOONGSON
 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook for Loongson2.  */
 
 static void
@@ -14854,6 +14879,7 @@ mips_dfa_post_advance_cycle (void)
   if (TUNE_LOONGSON_2EF)
     mips_ls2_dfa_post_advance_cycle (curr_state);
 }
+#endif
 
 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD.  This should
    be as wide as the scheduling freedom in the DFA.  */
@@ -14951,6 +14977,7 @@ mips_macc_chains_reorder (rtx_insn **ready, int nready)
 	}
 }
 
+#ifdef MIPS_SUPPORT_LEGACY
 /* The last instruction to be scheduled.  */
 static rtx_insn *vr4130_last_insn;
 
@@ -15050,6 +15077,7 @@ vr4130_reorder (rtx_insn **ready, int nready)
   if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
     mips_promote_ready (ready, nready - 2, nready - 1);
 }
+#endif
 
 /* Record whether last 74k AGEN instruction was a load or store.  */
 static enum attr_type mips_last_74k_agen_insn = TYPE_UNKNOWN;
@@ -15131,14 +15159,18 @@ mips_sched_init (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
 		 int max_ready ATTRIBUTE_UNUSED)
 {
   mips_macc_chains_last_hilo = 0;
+#ifdef MIPS_SUPPORT_LEGACY
   vr4130_last_insn = 0;
+#endif
   mips_74k_agen_init (NULL);
 
+#ifdef MIPS_SUPPORT_LOONGSON
   /* When scheduling for Loongson2, branch instructions go to ALU1,
      therefore basic block is most likely to start with round-robin counter
      pointed to ALU2.  */
   mips_ls2.alu1_turn_p = false;
   mips_ls2.falu1_turn_p = true;
+#endif
 }
 
 /* Subroutine used by TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2.  */
@@ -15152,11 +15184,13 @@ mips_sched_reorder_1 (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
       && *nreadyp > 0)
     mips_macc_chains_reorder (ready, *nreadyp);
 
+#ifdef MIPS_SUPPORT_LEGACY
   if (reload_completed
       && TUNE_MIPS4130
       && !TARGET_VR4130_ALIGN
       && *nreadyp > 1)
     vr4130_reorder (ready, *nreadyp);
+#endif
 
   if (TUNE_74K)
     mips_74k_agen_reorder (ready, *nreadyp);
@@ -15182,6 +15216,7 @@ mips_sched_reorder2 (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
   return cached_can_issue_more;
 }
 
+#ifdef MIPS_SUPPORT_LOONGSON
 /* Update round-robin counters for ALU1/2 and FALU1/2.  */
 
 static void
@@ -15212,6 +15247,7 @@ mips_ls2_variable_issue (rtx_insn *insn)
   if (recog_memoized (insn) >= 0)
     mips_ls2.cycle_has_multi_p |= (get_attr_type (insn) == TYPE_MULTI);
 }
+#endif
 
 /* Implement TARGET_SCHED_VARIABLE_ISSUE.  */
 
@@ -15226,11 +15262,15 @@ mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
 	more--;
       if (!reload_completed && TUNE_MACC_CHAINS)
 	mips_macc_chains_record (insn);
+#ifdef MIPS_SUPPORT_LEGACY
       vr4130_last_insn = insn;
+#endif
       if (TUNE_74K)
 	mips_74k_agen_init (insn);
+#ifdef MIPS_SUPPORT_LOONGSON
       else if (TUNE_LOONGSON_2EF)
 	mips_ls2_variable_issue (insn);
+#endif
     }
 
   /* Instructions of type 'multi' should all be split before
@@ -15335,17 +15375,25 @@ struct mips_builtin_description {
 };
 
 AVAIL_ALL (hard_float, TARGET_HARD_FLOAT_ABI)
+#ifdef MIPS_SUPPORT_PS_3D
 AVAIL_NON_MIPS16 (paired_single, TARGET_PAIRED_SINGLE_FLOAT)
 AVAIL_NON_MIPS16 (sb1_paired_single, TARGET_SB1 && TARGET_PAIRED_SINGLE_FLOAT)
 AVAIL_NON_MIPS16 (mips3d, TARGET_MIPS3D)
+#endif
+#ifdef MIPS_SUPPORT_DSP
 AVAIL_NON_MIPS16 (dsp, TARGET_DSP)
 AVAIL_NON_MIPS16 (dspr2, TARGET_DSPR2)
 AVAIL_NON_MIPS16 (dsp_32, !TARGET_64BIT && TARGET_DSP)
 AVAIL_NON_MIPS16 (dsp_64, TARGET_64BIT && TARGET_DSP)
 AVAIL_NON_MIPS16 (dspr2_32, !TARGET_64BIT && TARGET_DSPR2)
+#endif
+#ifdef MIPS_SUPPORT_LOONGSON
 AVAIL_NON_MIPS16 (loongson, TARGET_LOONGSON_MMI)
+#endif
 AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN)
+#ifdef MIPS_SUPPORT_MSA
 AVAIL_NON_MIPS16 (msa, TARGET_MSA)
+#endif
 
 /* Construct a mips_builtin_description from the given arguments.
 
@@ -15511,6 +15559,7 @@ AVAIL_NON_MIPS16 (msa, TARGET_MSA)
     "__builtin_msa_" #INSN,  MIPS_BUILTIN_DIRECT_NO_TARGET,		\
     FUNCTION_TYPE, mips_builtin_avail_msa, false }
 
+#ifdef MIPS_SUPPORT_DSP
 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
@@ -15519,7 +15568,9 @@ AVAIL_NON_MIPS16 (msa, TARGET_MSA)
 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
 #define CODE_FOR_mips_mult CODE_FOR_mulsidi3_32bit
 #define CODE_FOR_mips_multu CODE_FOR_umulsidi3_32bit
+#endif
 
+#ifdef MIPS_SUPPORT_LOONGSON
 #define CODE_FOR_loongson_packsswh CODE_FOR_vec_pack_ssat_v2si
 #define CODE_FOR_loongson_packsshb CODE_FOR_vec_pack_ssat_v4hi
 #define CODE_FOR_loongson_packushb CODE_FOR_vec_pack_usat_v4hi
@@ -15550,7 +15601,9 @@ AVAIL_NON_MIPS16 (msa, TARGET_MSA)
 #define CODE_FOR_loongson_psubsb CODE_FOR_sssubv8qi3
 #define CODE_FOR_loongson_psubush CODE_FOR_ussubv4hi3
 #define CODE_FOR_loongson_psubusb CODE_FOR_ussubv8qi3
+#endif
 
+#ifdef MIPS_SUPPORT_MSA
 #define CODE_FOR_msa_adds_s_b CODE_FOR_ssaddv16qi3
 #define CODE_FOR_msa_adds_s_h CODE_FOR_ssaddv8hi3
 #define CODE_FOR_msa_adds_s_w CODE_FOR_ssaddv4si3
@@ -15747,6 +15800,7 @@ AVAIL_NON_MIPS16 (msa, TARGET_MSA)
 #define CODE_FOR_msa_ldi_h CODE_FOR_msa_ldiv8hi
 #define CODE_FOR_msa_ldi_w CODE_FOR_msa_ldiv4si
 #define CODE_FOR_msa_ldi_d CODE_FOR_msa_ldiv2di
+#endif
 
 static const struct mips_builtin_description mips_builtins[] = {
 #define MIPS_GET_FCSR 0
@@ -15754,6 +15808,7 @@ static const struct mips_builtin_description mips_builtins[] = {
 #define MIPS_SET_FCSR 1
   DIRECT_NO_TARGET_BUILTIN (set_fcsr, MIPS_VOID_FTYPE_USI, hard_float),
 
+#ifdef MIPS_SUPPORT_PS_3D
   DIRECT_BUILTIN_PURE (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
   DIRECT_BUILTIN_PURE (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
   DIRECT_BUILTIN_PURE (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
@@ -15787,7 +15842,9 @@ static const struct mips_builtin_description mips_builtins[] = {
 
   /* Built-in functions for the SB-1 processor.  */
   DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, sb1_paired_single),
+#endif
 
+#ifdef MIPS_SUPPORT_DSP
   /* Built-in functions for the DSP ASE (32-bit and 64-bit).  */
   DIRECT_BUILTIN_PURE (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
   DIRECT_BUILTIN_PURE (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
@@ -15933,7 +15990,9 @@ static const struct mips_builtin_description mips_builtins[] = {
   DIRECT_BUILTIN_PURE (dpaqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
   DIRECT_BUILTIN_PURE (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
   DIRECT_BUILTIN_PURE (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
+#endif
 
+#ifdef MIPS_SUPPORT_LOONGSON
   /* Builtin functions for ST Microelectronics Loongson-2E/2F cores.  */
   LOONGSON_BUILTIN (packsswh, MIPS_V4HI_FTYPE_V2SI_V2SI),
   LOONGSON_BUILTIN (packsshb, MIPS_V8QI_FTYPE_V4HI_V4HI),
@@ -16034,10 +16093,12 @@ static const struct mips_builtin_description mips_builtins[] = {
   LOONGSON_BUILTIN_SUFFIX (punpcklbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
   LOONGSON_BUILTIN_SUFFIX (punpcklhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
   LOONGSON_BUILTIN_SUFFIX (punpcklwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
+#endif
 
   /* Sundry other built-in functions.  */
   DIRECT_NO_TARGET_BUILTIN (cache, MIPS_VOID_FTYPE_SI_CVPOINTER, cache),
 
+#ifdef MIPS_SUPPORT_MSA
   /* Built-in functions for MSA.  */
   MSA_BUILTIN_PURE (sll_b, MIPS_V16QI_FTYPE_V16QI_V16QI),
   MSA_BUILTIN_PURE (sll_h, MIPS_V8HI_FTYPE_V8HI_V8HI),
@@ -16569,6 +16630,7 @@ static const struct mips_builtin_description mips_builtins[] = {
   MSA_NO_TARGET_BUILTIN (ctcmsa, MIPS_VOID_FTYPE_UQI_SI),
   MSA_BUILTIN_PURE (cfcmsa, MIPS_SI_FTYPE_UQI),
   MSA_BUILTIN_PURE (move_v, MIPS_V16QI_FTYPE_V16QI),
+#endif
 };
 
 /* Index I is the function declaration for mips_builtins[I], or null if the
@@ -16739,20 +16801,19 @@ mips_builtin_decl (unsigned int code, bool initialize_p ATTRIBUTE_UNUSED)
 /* Implement TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION.  */
 
 static tree
-mips_builtin_vectorized_function (unsigned int fn, tree type_out, tree type_in)
+mips_builtin_vectorized_function (unsigned int fn ATTRIBUTE_UNUSED,
+				  tree type_out, tree type_in)
 {
-  machine_mode in_mode, out_mode;
-  int in_n, out_n;
-
   if (TREE_CODE (type_out) != VECTOR_TYPE
       || TREE_CODE (type_in) != VECTOR_TYPE
       || !ISA_HAS_MSA)
     return NULL_TREE;
 
-  out_mode = TYPE_MODE (TREE_TYPE (type_out));
-  out_n = TYPE_VECTOR_SUBPARTS (type_out);
-  in_mode = TYPE_MODE (TREE_TYPE (type_in));
-  in_n = TYPE_VECTOR_SUBPARTS (type_in);
+#ifdef MIPS_SUPPORT_MSA
+  machine_mode out_mode = TYPE_MODE (TREE_TYPE (type_out));
+  int out_n = TYPE_VECTOR_SUBPARTS (type_out);
+  machine_mode in_mode = TYPE_MODE (TREE_TYPE (type_in));
+  int in_n = TYPE_VECTOR_SUBPARTS (type_in);
 
   /* INSN is the name of the associated instruction pattern, without
      the leading CODE_FOR_.  */
@@ -16774,6 +16835,7 @@ mips_builtin_vectorized_function (unsigned int fn, tree type_out, tree type_in)
     default:
       break;
     }
+#endif
 
   return NULL_TREE;
 }
@@ -16804,10 +16866,11 @@ static rtx
 mips_expand_builtin_insn (enum insn_code icode, unsigned int nops,
 			  struct expand_operand *ops, bool has_target_p)
 {
-  machine_mode imode;
+  machine_mode imode ATTRIBUTE_UNUSED;
   int rangelo = 0, rangehi = 0, error_opno = 0;
-  rtx sireg;
+  rtx sireg ATTRIBUTE_UNUSED;
 
+#ifdef MIPS_SUPPORT_MSA
   switch (icode)
     {
     /* The third operand of these instructions is in SImode, so we need to
@@ -17092,6 +17155,7 @@ mips_expand_builtin_insn (enum insn_code icode, unsigned int nops,
     default:
       break;
   }
+#endif
 
   if (error_opno != 0)
     {
@@ -17160,6 +17224,7 @@ mips_expand_builtin_direct (enum insn_code icode, rtx target, tree exp,
   return mips_expand_builtin_insn (icode, opno, ops, has_target_p);
 }
 
+#ifdef MIPS_SUPPORT_PS_3D
 /* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps
    function; TYPE says which.  EXP is the CALL_EXPR that calls the
    function, ICODE is the instruction that should be used to compare
@@ -17190,6 +17255,7 @@ mips_expand_builtin_movtf (enum mips_builtin_type type,
   return mips_expand_builtin_insn (CODE_FOR_mips_cond_move_tf_ps,
 				   4, ops, true);
 }
+#endif
 
 /* Expand an MSA built-in for a compare and branch instruction specified by
    ICODE, set a general-purpose register to 1 if the branch was taken,
@@ -17273,7 +17339,7 @@ mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
 			     enum insn_code icode, enum mips_fp_condition cond,
 			     rtx target, tree exp)
 {
-  rtx offset, condition, cmp_result;
+  rtx offset ATTRIBUTE_UNUSED, condition, cmp_result;
 
   if (target == 0 || GET_MODE (target) != SImode)
     target = gen_reg_rtx (SImode);
@@ -17290,12 +17356,14 @@ mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
       return mips_builtin_branch_and_move (condition, target,
 					   const0_rtx, const1_rtx);
 
+#ifdef MIPS_SUPPORT_PS_3D
     case MIPS_BUILTIN_CMP_UPPER:
     case MIPS_BUILTIN_CMP_LOWER:
       offset = GEN_INT (builtin_type == MIPS_BUILTIN_CMP_UPPER);
       condition = gen_single_cc (cmp_result, offset);
       return mips_builtin_branch_and_move (condition, target,
 					   const1_rtx, const0_rtx);
+#endif
 
     default:
       condition = gen_rtx_NE (VOIDmode, cmp_result, const0_rtx);
@@ -17304,6 +17372,7 @@ mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
     }
 }
 
+#ifdef MIPS_SUPPORT_DSP
 /* Expand a bposge built-in function of type BUILTIN_TYPE.  TARGET,
    if nonnull, suggests a good place to put the boolean result.  */
 
@@ -17327,6 +17396,7 @@ mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target)
   return mips_builtin_branch_and_move (condition, target,
 				       const1_rtx, const0_rtx);
 }
+#endif
 
 /* Implement TARGET_EXPAND_BUILTIN.  */
 
@@ -17358,10 +17428,12 @@ mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
     case MIPS_BUILTIN_DIRECT_NO_TARGET:
       return mips_expand_builtin_direct (d->icode, target, exp, false);
 
+#ifdef MIPS_SUPPORT_PS_3D
     case MIPS_BUILTIN_MOVT:
     case MIPS_BUILTIN_MOVF:
       return mips_expand_builtin_movtf (d->builtin_type, d->icode,
 					d->cond, target, exp);
+#endif
 
     case MIPS_BUILTIN_CMP_ANY:
     case MIPS_BUILTIN_CMP_ALL:
@@ -17374,8 +17446,10 @@ mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
     case MIPS_BUILTIN_MSA_TEST_BRANCH:
       return mips_expand_builtin_msa_test_branch (d->icode, exp);
 
+#ifdef MIPS_SUPPORT_DSP
     case MIPS_BUILTIN_BPOSGE32:
       return mips_expand_builtin_bposge (d->builtin_type, target);
+#endif
     }
   gcc_unreachable ();
 }
@@ -20525,7 +20599,9 @@ mips_option_override (void)
   if (TARGET_HARD_FLOAT_ABI && TARGET_MIPS5900)
     REAL_MODE_FORMAT (SFmode) = &spu_single_format;
 
+#ifdef MIPS_SUPPORT_FRAME_HEADER_OPT
   mips_register_frame_header_opt ();
+#endif
 }
 
 /* Swap the register information for registers I and I + 1, which
@@ -20558,9 +20634,11 @@ mips_conditional_register_usage (void)
 
   if (ISA_HAS_DSP)
     {
+#ifdef MIPS_SUPPORT_DSP
       /* These DSP control register fields are global.  */
       global_regs[CCDSP_PO_REGNUM] = 1;
       global_regs[CCDSP_SC_REGNUM] = 1;
+#endif
     }
   else
     accessible_reg_set &= ~reg_class_contents[DSP_ACC_REGS];
@@ -21469,6 +21547,7 @@ mips_expand_vselect_vconcat (rtx target, rtx op0, rtx op1,
   return mips_expand_vselect (target, x, perm, nelt);
 }
 
+#ifdef MIPS_SUPPORT_LOONGSON
 /* Recognize patterns for even-odd extraction.  */
 
 static bool
@@ -21619,11 +21698,12 @@ mips_expand_vpc_loongson_bcast (struct expand_vec_perm_d *d)
   emit_move_insn (d->target, gen_lowpart (V8QImode, t1));
   return true;
 }
+#endif
 
 /* Construct (set target (vec_select op0 (parallel selector))) and
    return true if that's a valid instruction in the active ISA.  */
 
-static bool
+static bool ATTRIBUTE_UNUSED
 mips_expand_msa_shuffle (struct expand_vec_perm_d *d)
 {
   rtx x, elts[MAX_VECT_LEN];
@@ -21683,14 +21763,18 @@ mips_expand_vec_perm_const_1 (struct expand_vec_perm_d *d)
 	return true;
     }
 
+#ifdef MIPS_SUPPORT_LOONGSON
   if (mips_expand_vpc_loongson_even_odd (d))
     return true;
   if (mips_expand_vpc_loongson_pshufh (d))
     return true;
   if (mips_expand_vpc_loongson_bcast (d))
     return true;
+#endif
+#ifdef MIPS_SUPPORT_MSA
   if (mips_expand_msa_shuffle (d))
     return true;
+#endif
   return false;
 }
 
@@ -21803,6 +21887,7 @@ mips_sched_reassociation_width (unsigned int opc ATTRIBUTE_UNUSED,
   return 1;
 }
 
+#ifdef MIPS_SUPPORT_MSA
 /* Expand an integral vector unpack operation.  */
 
 void
@@ -21922,6 +22007,7 @@ mips_msa_vec_parallel_const_half (machine_mode mode, bool high_p)
 
   return gen_rtx_PARALLEL (VOIDmode, v);
 }
+#endif
 
 /* A subroutine of mips_expand_vec_init, match constant vector elements.  */
 
@@ -21948,12 +22034,14 @@ mips_expand_vi_broadcast (machine_mode vmode, rtx target, rtx elt)
   t1 = gen_reg_rtx (vmode);
   switch (vmode)
     {
+#ifdef MIPS_SUPPORT_LOONGSON
     case E_V8QImode:
       emit_insn (gen_loongson_vec_init1_v8qi (t1, elt));
       break;
     case E_V4HImode:
       emit_insn (gen_loongson_vec_init1_v4hi (t1, elt));
       break;
+#endif
     default:
       gcc_unreachable ();
     }
@@ -21982,7 +22070,7 @@ mips_gen_const_int_vector (machine_mode mode, HOST_WIDE_INT val)
 /* Return a vector of repeated 4-element sets generated from
    immediate VAL in mode MODE.  */
 
-static rtx
+static rtx ATTRIBUTE_UNUSED
 mips_gen_const_int_vector_shuffle (machine_mode mode, int val)
 {
   int nunits = GET_MODE_NUNITS (mode);
@@ -22021,6 +22109,7 @@ mips_expand_vi_constant (machine_mode vmode, unsigned nelt,
 }
 
 
+#ifdef MIPS_SUPPORT_LOONGSON
 /* A subroutine of mips_expand_vec_init, expand via pinsrh.  */
 
 static void
@@ -22031,6 +22120,7 @@ mips_expand_vi_loongson_one_pinsrh (rtx target, rtx vals, unsigned one_var)
   emit_insn (gen_vec_setv4hi (target, target, XVECEXP (vals, 0, one_var),
 			      GEN_INT (one_var)));
 }
+#endif
 
 /* A subroutine of mips_expand_vec_init, expand anything via memory.  */
 
@@ -22062,7 +22152,10 @@ mips_expand_vector_init (rtx target, rtx vals)
   machine_mode vmode = GET_MODE (target);
   machine_mode imode = GET_MODE_INNER (vmode);
   unsigned i, nelt = GET_MODE_NUNITS (vmode);
-  unsigned nvar = 0, one_var = -1u;
+  unsigned nvar = 0;
+#ifdef MIPS_SUPPORT_LOONGSON
+  unsigned one_var = -1u;
+#endif
   bool all_same = true;
   rtx x;
 
@@ -22070,7 +22163,11 @@ mips_expand_vector_init (rtx target, rtx vals)
     {
       x = XVECEXP (vals, 0, i);
       if (!mips_constant_elt_p (x))
+#ifdef MIPS_SUPPORT_LOONGSON
 	nvar++, one_var = i;
+#else
+	nvar++;
+#endif
       if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
 	all_same = false;
     }
@@ -22117,6 +22214,7 @@ mips_expand_vector_init (rtx target, rtx vals)
 	      mips_emit_move (target, gen_rtx_VEC_DUPLICATE (vmode, temp));
 	      break;
 
+#ifdef MIPS_SUPPORT_MSA
 	    case E_V4SFmode:
 	      emit_insn (gen_msa_splati_w_f_scalar (target, temp));
 	      break;
@@ -22124,11 +22222,13 @@ mips_expand_vector_init (rtx target, rtx vals)
 	    case E_V2DFmode:
 	      emit_insn (gen_msa_splati_d_f_scalar (target, temp));
 	      break;
+#endif
 
 	    default:
 	      gcc_unreachable ();
 	    }
 	}
+#if defined (MIPS_SUPPORT_MSA) || defined (MIPS_SUPPORT_LOONGSON)
       else
 	{
 	  emit_move_insn (target, CONST0_RTX (vmode));
@@ -22168,6 +22268,7 @@ mips_expand_vector_init (rtx target, rtx vals)
 		}
 	    }
 	}
+#endif
       return;
     }
 
@@ -22198,12 +22299,14 @@ mips_expand_vector_init (rtx target, rtx vals)
       return;
     }
 
+#ifdef MIPS_SUPPORT_LOONGSON
   /* If we've only got one non-variable V4HImode, use PINSRH.  */
   if (nvar == 1 && vmode == V4HImode)
     {
       mips_expand_vi_loongson_one_pinsrh (target, vals, one_var);
       return;
     }
+#endif
 
   mips_expand_vi_general (vmode, imode, nelt, nvar, target, vals);
 }
@@ -22215,7 +22318,10 @@ mips_expand_vec_reduc (rtx target, rtx in, rtx (*gen)(rtx, rtx, rtx))
 {
   machine_mode vmode = GET_MODE (in);
   unsigned char perm2[2];
-  rtx last, next, fold, x;
+  rtx last, fold;
+#ifdef MIPS_SUPPORT_LOONGSON
+  rtx next, x;
+#endif
   bool ok;
 
   last = in;
@@ -22233,6 +22339,7 @@ mips_expand_vec_reduc (rtx target, rtx in, rtx (*gen)(rtx, rtx, rtx))
       gcc_assert (ok);
       break;
 
+#ifdef MIPS_SUPPORT_LOONGSON
     case E_V2SImode:
       /* Use interleave to produce { H, L } op { H, H }.  */
       emit_insn (gen_loongson_punpckhwd (fold, last, last));
@@ -22271,6 +22378,7 @@ mips_expand_vec_reduc (rtx target, rtx in, rtx (*gen)(rtx, rtx, rtx))
       x = force_reg (SImode, GEN_INT (8));
       emit_insn (gen_vec_shr_v8qi (fold, last, x));
       break;
+#endif
 
     default:
       gcc_unreachable ();
@@ -22379,10 +22487,12 @@ mips_expand_msa_cmp (rtx dest, enum rtx_code cond, rtx op0, rtx op1)
 	case LTGT: cond = NE; break;
 	case UNGE: cond = UNLE; std::swap (op0, op1); break;
 	case UNGT: cond = UNLT; std::swap (op0, op1); break;
+#ifdef MIPS_SUPPORT_MSA
 	case LE: unspec = UNSPEC_MSA_FSLE; break;
 	case LT: unspec = UNSPEC_MSA_FSLT; break;
 	case GE: unspec = UNSPEC_MSA_FSLE; std::swap (op0, op1); break;
 	case GT: unspec = UNSPEC_MSA_FSLT; std::swap (op0, op1); break;
+#endif
 	default:
 	  gcc_unreachable ();
 	}
@@ -22700,10 +22810,14 @@ mips_asm_file_end (void)
 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
 #undef TARGET_SCHED_ISSUE_RATE
 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
-#undef TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN
-#define TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN mips_init_dfa_post_cycle_insn
-#undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
-#define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE mips_dfa_post_advance_cycle
+
+#ifdef MIPS_SUPPORT_LOONGSON
+# undef TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN
+# define TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN mips_init_dfa_post_cycle_insn
+# undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
+# define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE mips_dfa_post_advance_cycle
+#endif
+
 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
   mips_multipass_dfa_lookahead
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index a44ccada0bc..c188cfdbeaa 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -24,6 +24,14 @@ along with GCC; see the file COPYING3.  If not see
 
 #include "config/vxworks-dummy.h"
 
+#define MIPS_SUPPORT_DSP 1
+#define MIPS_SUPPORT_PS_3D 1
+#define MIPS_SUPPORT_MSA 1
+#define MIPS_SUPPORT_LOONGSON 1
+#define MIPS_SUPPORT_MICROMIPS 1
+#define MIPS_SUPPORT_LEGACY 1
+#define MIPS_SUPPORT_FRAME_HEADER_OPT 1
+
 #ifdef GENERATOR_FILE
 /* This is used in some insn conditions, so needs to be declared, but
    does not need to be defined.  */
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 1c8b3b98b20..089faf86c2f 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -21,59 +21,6 @@
 ;; along with GCC; see the file COPYING3.  If not see
 ;; <http://www.gnu.org/licenses/>.
 
-(define_enum "processor" [
-  r3000
-  4kc
-  4kp
-  5kc
-  5kf
-  20kc
-  24kc
-  24kf2_1
-  24kf1_1
-  74kc
-  74kf2_1
-  74kf1_1
-  74kf3_2
-  loongson_2e
-  loongson_2f
-  gs464
-  gs464e
-  gs264e
-  m4k
-  octeon
-  octeon2
-  octeon3
-  r3900
-  r6000
-  r4000
-  r4100
-  r4111
-  r4120
-  r4130
-  r4300
-  r4600
-  r4650
-  r4700
-  r5000
-  r5400
-  r5500
-  r5900
-  r7000
-  r8000
-  r9000
-  r10000
-  sb1
-  sb1a
-  sr71000
-  xlr
-  xlp
-  p5600
-  m5100
-  i6400
-  p6600
-])
-
 (define_c_enum "unspec" [
   ;; Unaligned accesses.
   UNSPEC_LOAD_LEFT
@@ -1160,38 +1107,6 @@
   (eq_attr "type" "ghost")
   "nothing")
 
-(include "i6400.md")
-(include "p5600.md")
-(include "m5100.md")
-(include "p6600.md")
-(include "4k.md")
-(include "5k.md")
-(include "20kc.md")
-(include "24k.md")
-(include "74k.md")
-(include "3000.md")
-(include "4000.md")
-(include "4100.md")
-(include "4130.md")
-(include "4300.md")
-(include "4600.md")
-(include "5000.md")
-(include "5400.md")
-(include "5500.md")
-(include "6000.md")
-(include "7000.md")
-(include "9000.md")
-(include "10000.md")
-(include "loongson2ef.md")
-(include "gs464.md")
-(include "gs464e.md")
-(include "gs264e.md")
-(include "octeon.md")
-(include "sb1.md")
-(include "sr71k.md")
-(include "xlr.md")
-(include "xlp.md")
-(include "generic.md")
 
 ;;
 ;;  ....................
@@ -7792,35 +7707,3 @@
 		   (any_extend:SI (match_dup 3)))])]
   "")
 
-
-;; Synchronization instructions.
-
-(include "sync.md")
-
-; The MIPS Paired-Single Floating Point and MIPS-3D Instructions.
-
-(include "mips-ps-3d.md")
-
-; The MIPS DSP Instructions.
-
-(include "mips-dsp.md")
-
-; The MIPS DSP REV 2 Instructions.
-
-(include "mips-dspr2.md")
-
-; MIPS fixed-point instructions.
-(include "mips-fixed.md")
-
-; microMIPS patterns.
-(include "micromips.md")
-
-; Loongson MultiMedia extensions Instructions (MMI) patterns.
-(include "loongson-mmi.md")
-
-; The MIPS MSA Instructions.
-(include "mips-msa.md")
-
-(define_c_enum "unspec" [
-  UNSPEC_ADDRESS_FIRST
-])
diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt
index 6af8037e9bd..2e647d703b4 100644
--- a/gcc/config/mips/mips.opt
+++ b/gcc/config/mips/mips.opt
@@ -28,7 +28,7 @@ EL
 Driver
 
 mabi=
-Target RejectNegative Joined Enum(mips_abi) Var(mips_abi) Init(MIPS_ABI_DEFAULT)
+Target RejectNegative Joined Enum(mips_abi) Var(mips_abi) Init(MIPS_ABI_DEFAULT) Condition(MIPS_SUPPORT_LEGACY)
 -mabi=ABI	Generate code that conforms to the given ABI.
 
 Enum
@@ -51,15 +51,15 @@ EnumValue
 Enum(mips_abi) String(eabi) Value(ABI_EABI)
 
 mabicalls
-Target Mask(ABICALLS)
+Target Mask(ABICALLS) Condition(MIPS_SUPPORT_LEGACY)
 Generate code that can be used in SVR4-style dynamic objects.
 
 mmad
-Target Var(TARGET_MAD)
+Target Var(TARGET_MAD) Condition(MIPS_SUPPORT_LEGACY)
 Use PMC-style 'mad' instructions.
 
 mimadd
-Target Mask(IMADD)
+Target Mask(IMADD) Condition(MIPS_SUPPORT_DSP)
 Use integer madd/msub instructions.
 
 march=
@@ -71,11 +71,11 @@ Target RejectNegative Joined UInteger Var(mips_branch_cost)
 -mbranch-cost=COST	Set the cost of branches to roughly COST instructions.
 
 mbranch-likely
-Target Mask(BRANCHLIKELY)
+Target Mask(BRANCHLIKELY) Condition(MIPS_SUPPORT_LEGACY)
 Use Branch Likely instructions, overriding the architecture default.
 
 mflip-mips16
-Target Var(TARGET_FLIP_MIPS16)
+Target Var(TARGET_FLIP_MIPS16) Condition(MIPS_SUPPORT_LEGACY)
 Switch on/off MIPS16 ASE on alternating functions for compiler testing.
 
 mcheck-zero-division
@@ -83,7 +83,7 @@ Target Mask(CHECK_ZERO_DIV)
 Trap on integer divide by zero.
 
 mcode-readable=
-Target RejectNegative Joined Enum(mips_code_readable_setting) Var(mips_code_readable) Init(CODE_READABLE_YES)
+Target RejectNegative Joined Enum(mips_code_readable_setting) Var(mips_code_readable) Init(CODE_READABLE_YES) Condition(MIPS_SUPPORT_LEGACY)
 -mcode-readable=SETTING	Specify when instructions are allowed to access code.
 
 Enum
@@ -100,7 +100,7 @@ EnumValue
 Enum(mips_code_readable_setting) String(no) Value(CODE_READABLE_NO)
 
 mdivide-breaks
-Target RejectNegative Mask(DIVIDE_BREAKS)
+Target RejectNegative Mask(DIVIDE_BREAKS) Condition(MIPS_SUPPORT_LEGACY)
 Use branch-and-break sequences to check for integer divide by zero.
 
 mdivide-traps
@@ -108,7 +108,7 @@ Target RejectNegative InverseMask(DIVIDE_BREAKS, DIVIDE_TRAPS)
 Use trap instructions to check for integer divide by zero.
 
 mdmx
-Target RejectNegative Var(TARGET_MDMX)
+Target RejectNegative Var(TARGET_MDMX) Condition(MIPS_SUPPORT_LEGACY)
 Allow the use of MDMX instructions.
 
 mdouble-float
@@ -120,14 +120,14 @@ Target Var(TARGET_DSP)
 Use MIPS-DSP instructions.
 
 mdspr2
-Target Var(TARGET_DSPR2)
+Target Var(TARGET_DSPR2) Condition(MIPS_SUPPORT_DSP)
 Use MIPS-DSP REV 2 instructions.
 
 mdebug
-Target Var(TARGET_DEBUG_MODE) Undocumented
+Target Var(TARGET_DEBUG_MODE) Undocumented Condition(MIPS_SUPPORT_LEGACY)
 
 mdebugd
-Target Var(TARGET_DEBUG_D_MODE) Undocumented
+Target Var(TARGET_DEBUG_D_MODE) Undocumented Condition(MIPS_SUPPORT_LEGACY)
 
 meb
 Target RejectNegative Mask(BIG_ENDIAN)
@@ -146,7 +146,7 @@ Target Var(TARGET_EVA)
 Use Enhanced Virtual Addressing instructions.
 
 mexplicit-relocs
-Target Mask(EXPLICIT_RELOCS)
+Target Mask(EXPLICIT_RELOCS) Condition(MIPS_SUPPORT_LEGACY)
 Use NewABI-style %reloc() assembly operators.
 
 mextern-sdata
@@ -154,15 +154,15 @@ Target Var(TARGET_EXTERN_SDATA) Init(1)
 Use -G for data that is not defined by the current object.
 
 mfix-24k
-Target Var(TARGET_FIX_24K)
+Target Var(TARGET_FIX_24K) Condition(MIPS_SUPPORT_LEGACY)
 Work around certain 24K errata.
 
 mfix-r4000
-Target Mask(FIX_R4000)
+Target Mask(FIX_R4000) Condition(MIPS_SUPPORT_LEGACY)
 Work around certain R4000 errata.
 
 mfix-r4400
-Target Mask(FIX_R4400)
+Target Mask(FIX_R4400) Condition(MIPS_SUPPORT_LEGACY)
 Work around certain R4400 errata.
 
 mfix-r5900
@@ -170,43 +170,43 @@ Target Mask(FIX_R5900)
 Work around the R5900 short loop erratum.
 
 mfix-rm7000
-Target Var(TARGET_FIX_RM7000)
+Target Var(TARGET_FIX_RM7000) Condition(MIPS_SUPPORT_LEGACY)
 Work around certain RM7000 errata.
 
 mfix-r10000
-Target Mask(FIX_R10000)
+Target Mask(FIX_R10000) Condition(MIPS_SUPPORT_LEGACY)
 Work around certain R10000 errata.
 
 mfix-sb1
-Target Var(TARGET_FIX_SB1)
+Target Var(TARGET_FIX_SB1) Condition(MIPS_SUPPORT_LEGACY)
 Work around errata for early SB-1 revision 2 cores.
 
 mfix-vr4120
-Target Var(TARGET_FIX_VR4120)
+Target Var(TARGET_FIX_VR4120) Condition(MIPS_SUPPORT_LEGACY)
 Work around certain VR4120 errata.
 
 mfix-vr4130
-Target Var(TARGET_FIX_VR4130)
+Target Var(TARGET_FIX_VR4130) Condition(MIPS_SUPPORT_LEGACY)
 Work around VR4130 mflo/mfhi errata.
 
 mfix4300
-Target Var(TARGET_4300_MUL_FIX)
+Target Var(TARGET_4300_MUL_FIX) Condition(MIPS_SUPPORT_LEGACY)
 Work around an early 4300 hardware bug.
 
 mfp-exceptions
-Target Var(TARGET_FP_EXCEPTIONS) Init(1)
+Target Var(TARGET_FP_EXCEPTIONS) Init(1) Condition(MIPS_SUPPORT_LEGACY)
 FP exceptions are enabled.
 
 mfp32
-Target RejectNegative InverseMask(FLOAT64)
+Target RejectNegative InverseMask(FLOAT64) Condition(MIPS_SUPPORT_LEGACY)
 Use 32-bit floating-point registers.
 
 mfpxx
-Target RejectNegative Mask(FLOATXX)
+Target RejectNegative Mask(FLOATXX) Condition(MIPS_SUPPORT_LEGACY)
 Conform to the o32 FPXX ABI.
 
 mfp64
-Target RejectNegative Mask(FLOAT64)
+Target RejectNegative Mask(FLOAT64) Condition(MIPS_SUPPORT_LEGACY)
 Use 64-bit floating-point registers.
 
 mflush-func=
@@ -214,11 +214,11 @@ Target RejectNegative Joined Var(mips_cache_flush_func) Init(CACHE_FLUSH_FUNC)
 -mflush-func=FUNC	Use FUNC to flush the cache before calling stack trampolines.
 
 mabs=
-Target RejectNegative Joined Enum(mips_ieee_754_value) Var(mips_abs) Init(MIPS_IEEE_754_DEFAULT)
+Target RejectNegative Joined Enum(mips_ieee_754_value) Var(mips_abs) Init(MIPS_IEEE_754_DEFAULT) Condition(MIPS_SUPPORT_LEGACY)
 -mabs=MODE	Select the IEEE 754 ABS/NEG instruction execution mode.
 
 mnan=
-Target RejectNegative Joined Enum(mips_ieee_754_value) Var(mips_nan) Init(MIPS_IEEE_754_DEFAULT)
+Target RejectNegative Joined Enum(mips_ieee_754_value) Var(mips_nan) Init(MIPS_IEEE_754_DEFAULT) Condition(MIPS_SUPPORT_LEGACY)
 -mnan=ENCODING	Select the IEEE 754 NaN data encoding.
 
 Enum
@@ -244,7 +244,7 @@ Target Var(TARGET_GPOPT) Init(1)
 Use GP-relative addressing to access small data.
 
 mplt
-Target Var(TARGET_PLT)
+Target Var(TARGET_PLT) Condition(MIPS_SUPPORT_LEGACY)
 When generating -mabicalls code, allow executables to use PLTs and copy relocations.
 
 mhard-float
@@ -252,27 +252,27 @@ Target RejectNegative InverseMask(SOFT_FLOAT_ABI, HARD_FLOAT_ABI)
 Allow the use of hardware floating-point ABI and instructions.
 
 minterlink-compressed
-Target Var(TARGET_INTERLINK_COMPRESSED) Init(0)
+Target Var(TARGET_INTERLINK_COMPRESSED) Init(0) Condition(MIPS_SUPPORT_LEGACY)
 Generate code that is link-compatible with MIPS16 and microMIPS code.
 
 minterlink-mips16
-Target Var(TARGET_INTERLINK_COMPRESSED) Init(0)
+Target Var(TARGET_INTERLINK_COMPRESSED) Init(0) Condition(MIPS_SUPPORT_LEGACY)
 An alias for minterlink-compressed provided for backward-compatibility.
 
 mips
-Target RejectNegative Joined ToLower Enum(mips_mips_opt_value) Var(mips_isa_option)
+Target RejectNegative Joined ToLower Enum(mips_mips_opt_value) Var(mips_isa_option) Condition(MIPS_SUPPORT_LEGACY)
 -mipsN	Generate code for ISA level N.
 
 mips16
-Target RejectNegative Mask(MIPS16)
+Target RejectNegative Mask(MIPS16) Condition(MIPS_SUPPORT_LEGACY)
 Generate MIPS16 code.
 
 mips3d
-Target RejectNegative Var(TARGET_MIPS3D)
+Target RejectNegative Var(TARGET_MIPS3D) Condition(MIPS_SUPPORT_LEGACY)
 Use MIPS-3D instructions.
 
 mllsc
-Target Mask(LLSC)
+Target Mask(LLSC) Condition(MIPS_SUPPORT_LEGACY)
 Use ll, sc and sync instructions.
 
 mlocal-sdata
@@ -284,15 +284,15 @@ Target Var(TARGET_LONG_CALLS)
 Use indirect calls.
 
 mlong32
-Target RejectNegative InverseMask(LONG64, LONG32)
+Target RejectNegative InverseMask(LONG64, LONG32) Condition(MIPS_SUPPORT_LEGACY)
 Use a 32-bit long type.
 
 mlong64
-Target RejectNegative Mask(LONG64)
+Target RejectNegative Mask(LONG64) Condition(MIPS_SUPPORT_LEGACY)
 Use a 64-bit long type.
 
 mmcount-ra-address
-Target Var(TARGET_MCOUNT_RA_ADDRESS)
+Target Var(TARGET_MCOUNT_RA_ADDRESS) Condition(MIPS_SUPPORT_LEGACY)
 Pass the address of the ra save location to _mcount in $12.
 
 mmemcpy
@@ -300,11 +300,11 @@ Target Mask(MEMCPY)
 Don't optimize block moves.
 
 mmicromips
-Target Mask(MICROMIPS)
+Target Mask(MICROMIPS) Condition(MIPS_SUPPORT_LEGACY)
 Use microMIPS instructions.
 
 mmsa
-Target Mask(MSA)
+Target Var(TARGET_MSA) Condition(MIPS_SUPPORT_MSA)
 Use MIPS MSA Extension instructions.
 
 mmt
@@ -324,23 +324,23 @@ Target RejectNegative
 Do not use a cache-flushing function before calling stack trampolines.
 
 mno-mdmx
-Target RejectNegative Var(TARGET_MDMX, 0)
+Target RejectNegative Var(TARGET_MDMX, 0) Condition(MIPS_SUPPORT_LEGACY)
 Do not use MDMX instructions.
 
 mno-mips16
-Target RejectNegative InverseMask(MIPS16)
+Target RejectNegative InverseMask(MIPS16) Condition(MIPS_SUPPORT_LEGACY)
 Generate normal-mode code.
 
 mno-mips3d
-Target RejectNegative Var(TARGET_MIPS3D, 0)
+Target RejectNegative Var(TARGET_MIPS3D, 0) Condition(MIPS_SUPPORT_LEGACY)
 Do not use MIPS-3D instructions.
 
 mpaired-single
-Target Mask(PAIRED_SINGLE_FLOAT)
+Target Mask(PAIRED_SINGLE_FLOAT) Condition(MIPS_SUPPORT_LEGACY)
 Use paired-single floating-point instructions.
 
 mr10k-cache-barrier=
-Target Joined RejectNegative Enum(mips_r10k_cache_barrier_setting) Var(mips_r10k_cache_barrier) Init(R10K_CACHE_BARRIER_NONE)
+Target Joined RejectNegative Enum(mips_r10k_cache_barrier_setting) Var(mips_r10k_cache_barrier) Init(R10K_CACHE_BARRIER_NONE) Condition(MIPS_SUPPORT_LEGACY)
 -mr10k-cache-barrier=SETTING	Specify when r10k cache barriers should be inserted.
 
 Enum
@@ -357,11 +357,11 @@ EnumValue
 Enum(mips_r10k_cache_barrier_setting) String(none) Value(R10K_CACHE_BARRIER_NONE)
 
 mrelax-pic-calls
-Target Mask(RELAX_PIC_CALLS)
+Target Mask(RELAX_PIC_CALLS) Condition(MIPS_SUPPORT_LEGACY)
 Try to allow the linker to turn PIC calls into direct calls.
 
 mshared
-Target Var(TARGET_SHARED) Init(1)
+Target Var(TARGET_SHARED) Init(1) Condition(MIPS_SUPPORT_LEGACY)
 When generating -mabicalls code, make the code suitable for use in shared libraries.
 
 msingle-float
@@ -369,7 +369,7 @@ Target RejectNegative Mask(SINGLE_FLOAT)
 Restrict the use of hardware floating-point instructions to 32-bit operations.
 
 msmartmips
-Target Mask(SMARTMIPS)
+Target Mask(SMARTMIPS) Condition(MIPS_SUPPORT_LEGACY)
 Use SmartMIPS instructions.
 
 msoft-float
@@ -377,7 +377,7 @@ Target RejectNegative Mask(SOFT_FLOAT_ABI)
 Prevent the use of all hardware floating-point instructions.
 
 msplit-addresses
-Target Mask(SPLIT_ADDRESSES)
+Target Mask(SPLIT_ADDRESSES) Condition(MIPS_SUPPORT_LEGACY)
 Optimize lui/addiu address loads.
 
 msym32
@@ -385,11 +385,11 @@ Target Var(TARGET_SYM32)
 Assume all symbols have 32-bit values.
 
 msynci
-Target Mask(SYNCI)
+Target Mask(SYNCI) Condition(MIPS_SUPPORT_LEGACY)
 Use synci instruction to invalidate i-cache.
 
 mlra
-Target Var(mips_lra_flag) Init(1) Save
+Target Var(mips_lra_flag) Init(1) Save Condition(MIPS_SUPPORT_LEGACY)
 Use LRA instead of reload.
 
 mlxc1-sxc1
@@ -425,30 +425,30 @@ Target Var(TARGET_GINV)
 Use Global INValidate (GINV) instructions.
 
 mvr4130-align
-Target Mask(VR4130_ALIGN)
+Target Mask(VR4130_ALIGN) Condition(MIPS_SUPPORT_LEGACY)
 Perform VR4130-specific alignment optimizations.
 
 mxgot
-Target Var(TARGET_XGOT)
+Target Var(TARGET_XGOT) Condition(MIPS_SUPPORT_LEGACY)
 Lift restrictions on GOT size.
 
 modd-spreg
-Target Mask(ODD_SPREG)
+Target Mask(ODD_SPREG) Condition(MIPS_SUPPORT_LEGACY)
 Enable use of odd-numbered single-precision registers.
 
 mframe-header-opt
-Target Var(flag_frame_header_optimization) Optimization
+Target Var(flag_frame_header_optimization) Optimization Condition(MIPS_SUPPORT_FRAME_HEADER_OPT)
 Optimize frame header.
 
 noasmopt
-Driver
+Driver Condition(MIPS_SUPPORT_LEGACY)
 
 mload-store-pairs
-Target Var(TARGET_LOAD_STORE_PAIRS) Init(1)
+Target Var(TARGET_LOAD_STORE_PAIRS) Init(1) Condition(MIPS_SUPPORT_LEGACY)
 Enable load/store bonding.
 
 mcompact-branches=
-Target RejectNegative JoinedOrMissing Var(mips_cb) Enum(mips_cb_setting) Init(MIPS_CB_OPTIMAL)
+Target RejectNegative JoinedOrMissing Var(mips_cb) Enum(mips_cb_setting) Init(MIPS_CB_OPTIMAL) Condition(MIPS_SUPPORT_LEGACY)
 Specify the compact branch usage policy.
 
 Enum
@@ -465,13 +465,13 @@ EnumValue
 Enum(mips_cb_setting) String(always) Value(MIPS_CB_ALWAYS)
 
 mloongson-mmi
-Target Mask(LOONGSON_MMI)
+Target Mask(LOONGSON_MMI) Condition(MIPS_SUPPORT_LOONGSON)
 Use Loongson MultiMedia extensions Instructions (MMI) instructions.
 
 mloongson-ext
-Target Mask(LOONGSON_EXT)
+Target Mask(LOONGSON_EXT) Condition(MIPS_SUPPORT_LOONGSON)
 Use Loongson EXTension (EXT) instructions.
 
 mloongson-ext2
-Target Var(TARGET_LOONGSON_EXT2)
+Target Var(TARGET_LOONGSON_EXT2) Condition(MIPS_SUPPORT_LOONGSON)
 Use Loongson EXTension R2 (EXT2) instructions.
