[v2,1/2] aarch64: Add support for mfloat8x{8|16}_t types
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Commit Message
Compared to v1, I've split changes that aren't used for the type definitions
into a separate patch. I've also added some tests, mostly along the lines
suggested by Richard S.
Bootstrapped and regression tested on aarch64; ok for master?
gcc/ChangeLog:
* config/aarch64/aarch64-builtins.cc
(aarch64_init_simd_builtin_types): Initialise FP8 simd types.
* config/aarch64/aarch64-builtins.h
(enum aarch64_type_qualifiers): Add qualifier_modal_float bit.
* config/aarch64/aarch64-simd-builtin-types.def:
Add Mfloat8x{8|16}_t types.
* config/aarch64/arm_neon.h: Add mfloat8x{8|16}_t typedefs.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/movv16qi_2.c: Test mfloat as well.
* gcc.target/aarch64/movv16qi_3.c: Ditto.
* gcc.target/aarch64/movv2x16qi_1.c: Ditto.
* gcc.target/aarch64/movv3x16qi_1.c: Ditto.
* gcc.target/aarch64/movv4x16qi_1.c: Ditto.
* gcc.target/aarch64/movv8qi_2.c: Ditto.
* gcc.target/aarch64/movv8qi_3.c: Ditto.
* gcc.target/aarch64/mfloat-init-1.c: New test.
Comments
Andrew Carlotti <andrew.carlotti@arm.com> writes:
> Compared to v1, I've split changes that aren't used for the type definitions
> into a separate patch. I've also added some tests, mostly along the lines
> suggested by Richard S.
>
> Bootstrapped and regression tested on aarch64; ok for master?
>
> gcc/ChangeLog:
>
> * config/aarch64/aarch64-builtins.cc
> (aarch64_init_simd_builtin_types): Initialise FP8 simd types.
> * config/aarch64/aarch64-builtins.h
> (enum aarch64_type_qualifiers): Add qualifier_modal_float bit.
> * config/aarch64/aarch64-simd-builtin-types.def:
> Add Mfloat8x{8|16}_t types.
> * config/aarch64/arm_neon.h: Add mfloat8x{8|16}_t typedefs.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/aarch64/movv16qi_2.c: Test mfloat as well.
> * gcc.target/aarch64/movv16qi_3.c: Ditto.
> * gcc.target/aarch64/movv2x16qi_1.c: Ditto.
> * gcc.target/aarch64/movv3x16qi_1.c: Ditto.
> * gcc.target/aarch64/movv4x16qi_1.c: Ditto.
> * gcc.target/aarch64/movv8qi_2.c: Ditto.
> * gcc.target/aarch64/movv8qi_3.c: Ditto.
> * gcc.target/aarch64/mfloat-init-1.c: New test.
OK, thanks.
Richard
> diff --git a/gcc/config/aarch64/aarch64-builtins.h b/gcc/config/aarch64/aarch64-builtins.h
> index e326fe666769cedd6c06d0752ed30b9359745ac9..00db7a74885db4d97ed365e8e3e2d7cf7d8410a4 100644
> --- a/gcc/config/aarch64/aarch64-builtins.h
> +++ b/gcc/config/aarch64/aarch64-builtins.h
> @@ -54,6 +54,8 @@ enum aarch64_type_qualifiers
> /* Lane indices selected in quadtuplets. - must be in range, and flipped for
> bigendian. */
> qualifier_lane_quadtup_index = 0x1000,
> + /* Modal FP types. */
> + qualifier_modal_float = 0x2000,
> };
>
> #define ENTRY(E, M, Q, G) E,
> diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc
> index 7d737877e0bf6c1f9eb53351a6085b0db16a04d6..432131c3b2d7cf4f788b79ce3d84c9e7554dc750 100644
> --- a/gcc/config/aarch64/aarch64-builtins.cc
> +++ b/gcc/config/aarch64/aarch64-builtins.cc
> @@ -1220,6 +1220,10 @@ aarch64_init_simd_builtin_types (void)
> aarch64_simd_types[Bfloat16x4_t].eltype = bfloat16_type_node;
> aarch64_simd_types[Bfloat16x8_t].eltype = bfloat16_type_node;
>
> + /* Init FP8 element types. */
> + aarch64_simd_types[Mfloat8x8_t].eltype = aarch64_mfp8_type_node;
> + aarch64_simd_types[Mfloat8x16_t].eltype = aarch64_mfp8_type_node;
> +
> for (i = 0; i < nelts; i++)
> {
> tree eltype = aarch64_simd_types[i].eltype;
> diff --git a/gcc/config/aarch64/aarch64-simd-builtin-types.def b/gcc/config/aarch64/aarch64-simd-builtin-types.def
> index 6111cd0d4fe1136feabb36a4077cf86d13b835e2..83b2da2e7dc0962c1e5957e25c8f6232c2148fe5 100644
> --- a/gcc/config/aarch64/aarch64-simd-builtin-types.def
> +++ b/gcc/config/aarch64/aarch64-simd-builtin-types.def
> @@ -52,3 +52,5 @@
> ENTRY (Float64x2_t, V2DF, none, 13)
> ENTRY (Bfloat16x4_t, V4BF, none, 14)
> ENTRY (Bfloat16x8_t, V8BF, none, 14)
> + ENTRY (Mfloat8x8_t, V8QI, modal_float, 13)
> + ENTRY (Mfloat8x16_t, V16QI, modal_float, 14)
> diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h
> index e376685489da055029def6b661132b5154886b57..730d9d3fa8158ef2d1d13c0f629e306e774145a0 100644
> --- a/gcc/config/aarch64/arm_neon.h
> +++ b/gcc/config/aarch64/arm_neon.h
> @@ -72,6 +72,9 @@ typedef __Poly16_t poly16_t;
> typedef __Poly64_t poly64_t;
> typedef __Poly128_t poly128_t;
>
> +typedef __Mfloat8x8_t mfloat8x8_t;
> +typedef __Mfloat8x16_t mfloat8x16_t;
> +
> typedef __fp16 float16_t;
> typedef float float32_t;
> typedef double float64_t;
> diff --git a/gcc/testsuite/gcc.target/aarch64/mfloat-init-1.c b/gcc/testsuite/gcc.target/aarch64/mfloat-init-1.c
> new file mode 100644
> index 0000000000000000000000000000000000000000..15a6b331fd3986476950e799d11bdef710193f1d
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/mfloat-init-1.c
> @@ -0,0 +1,5 @@
> +/* { dg-do assemble } */
> +/* { dg-options "-O --save-temps" } */
> +
> +/* { dg-error "invalid conversion to type 'mfloat8_t" "" {target *-*-*} 0 } */
> +__Mfloat8x8_t const_mf8x8 () { return (__Mfloat8x8_t) { 1, 1, 1, 1, 1, 1, 1, 1 }; }
> diff --git a/gcc/testsuite/gcc.target/aarch64/movv16qi_2.c b/gcc/testsuite/gcc.target/aarch64/movv16qi_2.c
> index 08a0a19b515134742fcb121e8cf6a19600f86075..39a06db0707538996fb5a3990ef53589d0210b17 100644
> --- a/gcc/testsuite/gcc.target/aarch64/movv16qi_2.c
> +++ b/gcc/testsuite/gcc.target/aarch64/movv16qi_2.c
> @@ -17,6 +17,7 @@ TEST_GENERAL (__Bfloat16x8_t)
> TEST_GENERAL (__Float16x8_t)
> TEST_GENERAL (__Float32x4_t)
> TEST_GENERAL (__Float64x2_t)
> +TEST_GENERAL (__Mfloat8x16_t)
>
> __Int8x16_t const_s8x8 () { return (__Int8x16_t) { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }; }
> __Int16x8_t const_s16x4 () { return (__Int16x8_t) { 1, 0, 1, 0, 1, 0, 1, 0 }; }
> diff --git a/gcc/testsuite/gcc.target/aarch64/movv16qi_3.c b/gcc/testsuite/gcc.target/aarch64/movv16qi_3.c
> index d43b994c1387bd7d9fb9517944d807e7f70b3c2a..082e95c017381597357cdd2a40fd732b449d369f 100644
> --- a/gcc/testsuite/gcc.target/aarch64/movv16qi_3.c
> +++ b/gcc/testsuite/gcc.target/aarch64/movv16qi_3.c
> @@ -22,6 +22,7 @@ TEST_VECTOR (__Bfloat16x8_t)
> TEST_VECTOR (__Float16x8_t)
> TEST_VECTOR (__Float32x4_t)
> TEST_VECTOR (__Float64x2_t)
> +TEST_VECTOR (__Mfloat8x16_t)
>
> /*
> ** test___Int8x16_t:
> diff --git a/gcc/testsuite/gcc.target/aarch64/movv2x16qi_1.c b/gcc/testsuite/gcc.target/aarch64/movv2x16qi_1.c
> index 90e3b426d3a19acc83ba3ddb0a79d138d2fd65d8..5aeb975b9a8d5c93f178d9ac14240b27f9438fc9 100644
> --- a/gcc/testsuite/gcc.target/aarch64/movv2x16qi_1.c
> +++ b/gcc/testsuite/gcc.target/aarch64/movv2x16qi_1.c
> @@ -19,6 +19,7 @@ TEST_VECTOR (float16x8x2_t)
> TEST_VECTOR (bfloat16x8x2_t)
> TEST_VECTOR (float32x4x2_t)
> TEST_VECTOR (float64x2x2_t)
> +TEST_VECTOR (mfloat8x16x2_t)
>
> /*
> ** mov_int8x16x2_t:
> diff --git a/gcc/testsuite/gcc.target/aarch64/movv3x16qi_1.c b/gcc/testsuite/gcc.target/aarch64/movv3x16qi_1.c
> index 070a596bf97e832f640f98f9207b6ef708841793..4c6f24f9f9a5be0339f8fd8be45b1db2bc362f4b 100644
> --- a/gcc/testsuite/gcc.target/aarch64/movv3x16qi_1.c
> +++ b/gcc/testsuite/gcc.target/aarch64/movv3x16qi_1.c
> @@ -19,6 +19,7 @@ TEST_VECTOR (float16x8x3_t)
> TEST_VECTOR (bfloat16x8x3_t)
> TEST_VECTOR (float32x4x3_t)
> TEST_VECTOR (float64x2x3_t)
> +TEST_VECTOR (mfloat8x16x3_t)
>
> /*
> ** mov_int8x16x3_t:
> diff --git a/gcc/testsuite/gcc.target/aarch64/movv4x16qi_1.c b/gcc/testsuite/gcc.target/aarch64/movv4x16qi_1.c
> index 6a517b4fe57f6841edf4488b4dabb920d2a21b2a..7e5dd866f6419c38d703ae412d161ea71934541b 100644
> --- a/gcc/testsuite/gcc.target/aarch64/movv4x16qi_1.c
> +++ b/gcc/testsuite/gcc.target/aarch64/movv4x16qi_1.c
> @@ -19,6 +19,7 @@ TEST_VECTOR (float16x8x4_t)
> TEST_VECTOR (bfloat16x8x4_t)
> TEST_VECTOR (float32x4x4_t)
> TEST_VECTOR (float64x2x4_t)
> +TEST_VECTOR (mfloat8x16x4_t)
>
> /*
> ** mov_int8x16x4_t:
> diff --git a/gcc/testsuite/gcc.target/aarch64/movv8qi_2.c b/gcc/testsuite/gcc.target/aarch64/movv8qi_2.c
> index 0d8576ffefbb8bfd2c11b8d971445ad4e6a86a61..27c6044e41e1ec369839357ffadb0ad697db459a 100644
> --- a/gcc/testsuite/gcc.target/aarch64/movv8qi_2.c
> +++ b/gcc/testsuite/gcc.target/aarch64/movv8qi_2.c
> @@ -17,6 +17,7 @@ TEST_GENERAL (__Bfloat16x4_t)
> TEST_GENERAL (__Float16x4_t)
> TEST_GENERAL (__Float32x2_t)
> TEST_GENERAL (__Float64x1_t)
> +TEST_GENERAL (__Mfloat8x8_t)
>
> __Int8x8_t const_s8x8 () { return (__Int8x8_t) { 1, 1, 1, 1, 1, 1, 1, 1 }; }
> __Int16x4_t const_s16x4 () { return (__Int16x4_t) { 1, 0, 1, 0 }; }
> diff --git a/gcc/testsuite/gcc.target/aarch64/movv8qi_3.c b/gcc/testsuite/gcc.target/aarch64/movv8qi_3.c
> index 1caa1a788c9dae92d84832e4c4940f4049ebff20..a213a0fbf81c4eb237e92c84e3e3dd240c672740 100644
> --- a/gcc/testsuite/gcc.target/aarch64/movv8qi_3.c
> +++ b/gcc/testsuite/gcc.target/aarch64/movv8qi_3.c
> @@ -22,6 +22,7 @@ TEST_VECTOR (__Bfloat16x4_t)
> TEST_VECTOR (__Float16x4_t)
> TEST_VECTOR (__Float32x2_t)
> TEST_VECTOR (__Float64x1_t)
> +TEST_VECTOR (__Mfloat8x8_t)
>
> /*
> ** test___Int8x8_t:
@@ -54,6 +54,8 @@ enum aarch64_type_qualifiers
/* Lane indices selected in quadtuplets. - must be in range, and flipped for
bigendian. */
qualifier_lane_quadtup_index = 0x1000,
+ /* Modal FP types. */
+ qualifier_modal_float = 0x2000,
};
#define ENTRY(E, M, Q, G) E,
@@ -1220,6 +1220,10 @@ aarch64_init_simd_builtin_types (void)
aarch64_simd_types[Bfloat16x4_t].eltype = bfloat16_type_node;
aarch64_simd_types[Bfloat16x8_t].eltype = bfloat16_type_node;
+ /* Init FP8 element types. */
+ aarch64_simd_types[Mfloat8x8_t].eltype = aarch64_mfp8_type_node;
+ aarch64_simd_types[Mfloat8x16_t].eltype = aarch64_mfp8_type_node;
+
for (i = 0; i < nelts; i++)
{
tree eltype = aarch64_simd_types[i].eltype;
@@ -52,3 +52,5 @@
ENTRY (Float64x2_t, V2DF, none, 13)
ENTRY (Bfloat16x4_t, V4BF, none, 14)
ENTRY (Bfloat16x8_t, V8BF, none, 14)
+ ENTRY (Mfloat8x8_t, V8QI, modal_float, 13)
+ ENTRY (Mfloat8x16_t, V16QI, modal_float, 14)
@@ -72,6 +72,9 @@ typedef __Poly16_t poly16_t;
typedef __Poly64_t poly64_t;
typedef __Poly128_t poly128_t;
+typedef __Mfloat8x8_t mfloat8x8_t;
+typedef __Mfloat8x16_t mfloat8x16_t;
+
typedef __fp16 float16_t;
typedef float float32_t;
typedef double float64_t;
new file mode 100644
@@ -0,0 +1,5 @@
+/* { dg-do assemble } */
+/* { dg-options "-O --save-temps" } */
+
+/* { dg-error "invalid conversion to type 'mfloat8_t" "" {target *-*-*} 0 } */
+__Mfloat8x8_t const_mf8x8 () { return (__Mfloat8x8_t) { 1, 1, 1, 1, 1, 1, 1, 1 }; }
@@ -17,6 +17,7 @@ TEST_GENERAL (__Bfloat16x8_t)
TEST_GENERAL (__Float16x8_t)
TEST_GENERAL (__Float32x4_t)
TEST_GENERAL (__Float64x2_t)
+TEST_GENERAL (__Mfloat8x16_t)
__Int8x16_t const_s8x8 () { return (__Int8x16_t) { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }; }
__Int16x8_t const_s16x4 () { return (__Int16x8_t) { 1, 0, 1, 0, 1, 0, 1, 0 }; }
@@ -22,6 +22,7 @@ TEST_VECTOR (__Bfloat16x8_t)
TEST_VECTOR (__Float16x8_t)
TEST_VECTOR (__Float32x4_t)
TEST_VECTOR (__Float64x2_t)
+TEST_VECTOR (__Mfloat8x16_t)
/*
** test___Int8x16_t:
@@ -19,6 +19,7 @@ TEST_VECTOR (float16x8x2_t)
TEST_VECTOR (bfloat16x8x2_t)
TEST_VECTOR (float32x4x2_t)
TEST_VECTOR (float64x2x2_t)
+TEST_VECTOR (mfloat8x16x2_t)
/*
** mov_int8x16x2_t:
@@ -19,6 +19,7 @@ TEST_VECTOR (float16x8x3_t)
TEST_VECTOR (bfloat16x8x3_t)
TEST_VECTOR (float32x4x3_t)
TEST_VECTOR (float64x2x3_t)
+TEST_VECTOR (mfloat8x16x3_t)
/*
** mov_int8x16x3_t:
@@ -19,6 +19,7 @@ TEST_VECTOR (float16x8x4_t)
TEST_VECTOR (bfloat16x8x4_t)
TEST_VECTOR (float32x4x4_t)
TEST_VECTOR (float64x2x4_t)
+TEST_VECTOR (mfloat8x16x4_t)
/*
** mov_int8x16x4_t:
@@ -17,6 +17,7 @@ TEST_GENERAL (__Bfloat16x4_t)
TEST_GENERAL (__Float16x4_t)
TEST_GENERAL (__Float32x2_t)
TEST_GENERAL (__Float64x1_t)
+TEST_GENERAL (__Mfloat8x8_t)
__Int8x8_t const_s8x8 () { return (__Int8x8_t) { 1, 1, 1, 1, 1, 1, 1, 1 }; }
__Int16x4_t const_s16x4 () { return (__Int16x4_t) { 1, 0, 1, 0 }; }
@@ -22,6 +22,7 @@ TEST_VECTOR (__Bfloat16x4_t)
TEST_VECTOR (__Float16x4_t)
TEST_VECTOR (__Float32x2_t)
TEST_VECTOR (__Float64x1_t)
+TEST_VECTOR (__Mfloat8x8_t)
/*
** test___Int8x8_t: