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[commit,master+OG11] amdgcn: Fix ICE generating CFI [PR103396]

Message ID b750751c-b9cd-f0cf-df86-b4c148c97dbe@codesourcery.com
State Committed
Commit 58d50a5dd6344179eebaeb6fd2f895e59463cf74
Headers show
Series [commit,master+OG11] amdgcn: Fix ICE generating CFI [PR103396] | expand

Commit Message

Andrew Stubbs Nov. 25, 2021, 4:59 p.m. UTC
If committed this patch to fix the amdgcn ICE reported in PR103396.

The problem was that it was mis-counting the number of registers to save 
when the link register was only clobbered implicitly by calls. The issue 
is easily fixed by adjusting the condition to match elsewhere in the 
same function.

Committed to master and backported to devel/omp/gcc-11. It should affect 
GCC 11.

amdgcn: Fix ICE generating CFI [PR103396]


	PR target/103396
	* config/gcn/gcn.c (move_callee_saved_registers): Ensure that the
	number of spilled registers is counted correctly.
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diff --git a/gcc/config/gcn/gcn.c b/gcc/config/gcn/gcn.c
index 75a9c576694..2bde88afc32 100644
--- a/gcc/config/gcn/gcn.c
+++ b/gcc/config/gcn/gcn.c
@@ -2785,7 +2785,7 @@  move_callee_saved_registers (rtx sp, machine_function *offsets,
 		int start = (regno == VGPR_REGNO (7) ? 64 : 0);
 		int count = MIN (saved_scalars - start, 64);
 		int add_lr = (regno == VGPR_REGNO (6)
-			      && df_regs_ever_live_p (LINK_REGNUM));
+			      && offsets->lr_needs_saving);
 		int lrdest = -1;
 		rtvec seq = rtvec_alloc (count + add_lr);