From patchwork Sun Sep 26 13:24:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dragan Mladjenovic X-Patchwork-Id: 45447 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 6F172385840A for ; Sun, 26 Sep 2021 13:26:21 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 6F172385840A DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1632662781; bh=Bq3OAy66LXx8H/6YIlQ5Nv1nW/1b/meziY3p/ih247s=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:Cc:From; b=ab3vmv+DrkNhWfx6R3KCxh2nhC/jjfqIQnbaCMv2TmDtaJavYHhlvp50q0hsNOwhp B97eayMIW7lThD0+P9eA0TLgbeRomrB3KkYHkpBURW3qWK9MqKX5BUsOeaDq/aI0xR xN6C3YVCYBCp5NjUXSz/DCm4BRtuKkZJccHPSsEg= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mailgw02.mediatek.com (mailgw02.mediatek.com [216.200.240.185]) by sourceware.org (Postfix) with ESMTPS id 8E3963858403; Sun, 26 Sep 2021 13:24:49 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 8E3963858403 X-UUID: 320096a04551470e8b710418c5d46c13-20210926 X-UUID: 320096a04551470e8b710418c5d46c13-20210926 Received: from mtkcas68.mediatek.inc [(172.29.94.19)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 2116990207; Sun, 26 Sep 2021 06:24:45 -0700 Received: from MTKMBS62N1.mediatek.inc (172.29.193.41) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sun, 26 Sep 2021 06:24:44 -0700 Received: from MTKMBS62N1.mediatek.inc ([fe80::697c:586d:7cff:34e7]) by MTKMBS62N1.mediatek.inc ([fe80::697c:586d:7cff:34e7%12]) with mapi id 15.00.1497.015; Sun, 26 Sep 2021 06:24:44 -0700 To: "gcc-patches@gcc.gnu.org" Subject: [RFC 1/7] Avoid references to register names in instruction output patterns. Thread-Topic: [RFC 1/7] Avoid references to register names in instruction output patterns. Thread-Index: AQHXstneSWaf24jQQEW0QL55ADB2cg== Date: Sun, 26 Sep 2021 13:24:44 +0000 Message-ID: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [172.29.193.239] MIME-Version: 1.0 X-Spam-Status: No, score=-13.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, HTML_MESSAGE, SPF_HELO_NONE, SPF_PASS, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-Content-Filtered-By: Mailman/MimeDel 2.1.29 X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Dragan Mladjenovic via Gcc-patches From: Dragan Mladjenovic Reply-To: Dragan Mladjenovic Cc: Jeff Law , Matthew Fortune , Jakub Jelinek , YunQiang Su , "Petar.Jovanovic@syrmia.com" , Faraz Shahbazker , Vince Del Vecchio Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" This allows us to choose the different names if needed in the future. gcc/ChangeLog: * config/mips/mips.c (mips_print_operand_punctuation): Handle '&' punctuation. (mips_output_probe_stack_range): Use '%.' instead of $0. * config/mips/mips.h (GLOBAL_POINTER_REGNUM): Move to ... * config/mips/mips.md (GLOBAL_POINTER_REGNUM): ... here. (trap, *conditional_trap_reg, *msac, *muls, *muls_di, msubsidi4): Use '%.' instead of $0. (clear_hazard_): Use '%&' instead of $31. --- gcc/config/mips/mips.c | 9 +++++++-- gcc/config/mips/mips.h | 4 ---- gcc/config/mips/mips.md | 17 +++++++++-------- 3 files changed, 16 insertions(+), 14 deletions(-) 3 files changed, 16 insertions(+), 14 deletions(-) diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index ce60c5500b7..ab63575eb26 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -8816,6 +8816,7 @@ mips_pop_asm_switch (struct mips_asm_switch *asm_switch) '^' Print the name of the pic call-through register (t9 or $25). '+' Print the name of the gp register (usually gp or $28). '$' Print the name of the stack pointer register (sp or $29). + '&' Print the name of the return register (ra or $31). ':' Print "c" to use the compact version if the delay slot is a nop. '!' Print "s" to use the short version if the delay slot contains a 16-bit instruction. @@ -8902,6 +8903,10 @@ mips_print_operand_punctuation (FILE *file, int ch) fputs (reg_names[STACK_POINTER_REGNUM], file); break; + case '&': + fputs (reg_names[RETURN_ADDR_REGNUM], file); + break; + case ':': /* When final_sequence is 0, the delay slot will be a nop. We can use the compact version where available. The %: formatter will @@ -12133,9 +12138,9 @@ mips_output_probe_stack_range (rtx reg1, rtx reg2) strcpy (tmp, "%(%" @@ -1860,7 +1861,7 @@ else if (TARGET_MIPS5500) return "msub\t%2,%3"; else - return "msac\t$0,%2,%3"; + return "msac\t%.,%2,%3"; } [(set_attr "type" "imadd") (set_attr "accum_in" "1") @@ -2060,7 +2061,7 @@ (clobber (match_scratch:SI 3 "=X,l"))] "ISA_HAS_MULS" "@ - muls\t$0,%1,%2 + muls\t%.,%1,%2 muls\t%0,%1,%2" [(set_attr "type" "imul,imul3") (set_attr "mode" "SI")]) @@ -2243,7 +2244,7 @@ (any_extend:DI (match_operand:SI 1 "register_operand" "d")) (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))] "!TARGET_64BIT && ISA_HAS_MULS" - "muls\t$0,%1,%2" + "muls\t%.,%1,%2" [(set_attr "type" "imul") (set_attr "mode" "SI")]) @@ -2268,7 +2269,7 @@ else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB) return "msub\t%1,%2"; else - return "msac\t$0,%1,%2"; + return "msac\t%.,%1,%2"; } [(set_attr "type" "imadd") (set_attr "accum_in" "3") @@ -5622,8 +5623,8 @@ { return "%(%addiu\t$31,$31,12\n" - "\tjr.hb\t$31\n" + "1:\taddiu\t%&,%&,12\n" + "\tjr.hb\t%&\n" "\tnop%>%)"; }