From patchwork Mon Oct 17 23:25:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jeff Law X-Patchwork-Id: 58962 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 8A935385841D for ; Mon, 17 Oct 2022 23:26:11 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 8A935385841D DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1666049171; bh=yGDNrlubAsyZYP3dwV9cccVW03/M9xcsyKBn3/hrcmI=; h=Date:To:Subject:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=Cmyb61DyUUsfE9tqO1sF3hsdNeJZ6Xxaj/Y+h/lFoSdOfnSzCh2VEN+U2DAx9lxkl JP7WyGdsvEflyCD3QWd7ttI8Q7Ql4R7g0j3PQFsW53ur9aAR8tiU2GUMec8N8fFJEB /4o02PncgwCVrorjxeHLX8yGdZUCQrQ7shaZZ6UY= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pl1-x62a.google.com (mail-pl1-x62a.google.com [IPv6:2607:f8b0:4864:20::62a]) by sourceware.org (Postfix) with ESMTPS id A096E3858D32 for ; Mon, 17 Oct 2022 23:25:42 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org A096E3858D32 Received: by mail-pl1-x62a.google.com with SMTP id l1so12157320pld.13 for ; Mon, 17 Oct 2022 16:25:42 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=subject:from:to:content-language:user-agent:mime-version:date :message-id:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=yGDNrlubAsyZYP3dwV9cccVW03/M9xcsyKBn3/hrcmI=; b=52GeCT8rTCEGKOcB69T0ozI9LD933g9vF1xUr9yqkM6aFWbmHR8w3n+PjTjcU+Iu/0 kRZn4eatHUdJYD+xRiayS4m4y/czArd2/3fnhonCtnTgwL8Hlpo/IoLbkhUZI0KA+8J7 YdSU/90EsTJJnyQZ4l38OSX3uzB++0oj+wBu8f5sIX4TDYXmq5l5lwldBEMrxUi57bsk hOd99VaxSeUsA6cVVVbGov9giOiPLKwjvwFMaheDbwWOICzbdw2OYHu31bRatMwz58sv Xt1s/bKUf9W4sx7DlynqS5ZL4Ff//lBtFIgrpyktCv/lfcWRkEt2DvmdPnKkcSyDINeL 2YsA== X-Gm-Message-State: ACrzQf31NMQSITMcSBPi8BCOhZVPU0bnTBRKpjSXxhIOBJCONUxZo45L 4j6Zv4RqM3ITiwTMbf5cTVpmQ8zAJKY= X-Google-Smtp-Source: AMsMyM6uPe4asdQAD9Df3PXHRjgyixBvsbGlRvdZgKlBb1hsS1HcIDuBksFwwR9ZAXsjviOAO8n/kw== X-Received: by 2002:a17:902:9005:b0:181:898b:646d with SMTP id a5-20020a170902900500b00181898b646dmr35798plp.97.1666049141160; Mon, 17 Oct 2022 16:25:41 -0700 (PDT) Received: from ?IPV6:2601:681:8600:13d0::f0a? ([2601:681:8600:13d0::f0a]) by smtp.gmail.com with ESMTPSA id i3-20020a17090ac40300b002036006d65bsm6736414pjt.39.2022.10.17.16.25.40 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 17 Oct 2022 16:25:40 -0700 (PDT) Message-ID: Date: Mon, 17 Oct 2022 17:25:39 -0600 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.3.1 Content-Language: en-US To: "gcc-patches@gcc.gnu.org" Subject: [committed] Add missing splitter for H8 X-Spam-Status: No, score=-8.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_NUMSUBJECT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Jeff Law via Gcc-patches From: Jeff Law Reply-To: Jeff Law Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" While testing a minor optimization on the H8 my builds failed due to failure to split a zero-extended memory load.    That particular pattern is a bit special on the H8 in that it's split at assembly time primarily to get the length computations correct.  Arguably that alternative should go away completely, but I haven't really looked into that. Anyway, with the final-asm split we obviously need to match a define_split somewhere.  But none was ever written after adding CCZN optimizations.  So if we had a zero extend of a memory operand and it was used to eliminate a compare, then we'd abort at final asm time. Regression tested (in conjunction with various other in-progress patches) on H8 without regressions. Installed on the trunk. Jeff commit 43ee3f64cb519f2675fa1771007d4aa3baba944f Author: Jeff Law Date: Mon Oct 17 19:19:25 2022 -0400 Add missing splitter for H8 While testing a minor optimization on the H8 my builds failed due to failure to split a zero-extended memory load. That particular pattern is a bit special on the H8 in that it's split at assembly time primarily to get the length computations correct. Arguably that alternative should go away completely, but I haven't really looked into that. Anyway, with the final-asm split we obviously need to match a define_split somewhere. But none was ever written after adding CCZN optimizations. So if we had a zero extend of a memory operand and it was used to eliminate a compare, then we'd abort at final asm time. Regression tested (in conjunction with various other in-progress patches) on H8 without regressions. gcc/ * config/h8300/extensions.md (CCZN setting zero extended load): Add missing splitter. diff --git a/gcc/config/h8300/extensions.md b/gcc/config/h8300/extensions.md index 74647c79cd8..7149dc0ac52 100644 --- a/gcc/config/h8300/extensions.md +++ b/gcc/config/h8300/extensions.md @@ -47,6 +47,24 @@ operands[2] = gen_rtx_REG (QImode, REGNO (operands[0])); }) +;; Similarly, but setting cczn. +(define_split + [(set (reg:CCZN CC_REG) + (compare:CCZN + (zero_extend:HI (match_operand:QI 1 "general_operand_src" "")) + (const_int 0))) + (set (match_operand:HI 0 "register_operand" "") + (zero_extend:HI (match_dup 1)))] + "!REG_P (operands[1]) && reload_completed" + [(parallel [(set (match_dup 2) (match_dup 1)) + (clobber (reg:CC CC_REG))]) + (parallel [(set (reg:CCZN CC_REG) + (compare:CCZN (zero_extend:HI (match_dup 2)) (const_int 0))) + (set (match_dup 0) (zero_extend:HI (match_dup 2)))])] + { + operands[2] = gen_rtx_REG (QImode, REGNO (operands[0])); + }) + (define_insn "*zero_extendqisi2" [(set (match_operand:SI 0 "register_operand" "=r,r") (zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]