[committed] Add missing splitter for H8
Commit Message
While testing a minor optimization on the H8 my builds failed due to
failure to split a zero-extended memory load. That particular pattern
is a bit special on the H8 in that it's split at assembly time primarily
to get the length computations correct. Arguably that alternative
should go away completely, but I haven't really looked into that.
Anyway, with the final-asm split we obviously need to match a
define_split somewhere. But none was ever written after adding CCZN
optimizations. So if we had a zero extend of a memory operand and it
was used to eliminate a compare, then we'd abort at final asm time.
Regression tested (in conjunction with various other in-progress
patches) on H8 without regressions.
Installed on the trunk.
Jeff
commit 43ee3f64cb519f2675fa1771007d4aa3baba944f
Author: Jeff Law <jeffreyalaw@gmail.com>
Date: Mon Oct 17 19:19:25 2022 -0400
Add missing splitter for H8
While testing a minor optimization on the H8 my builds failed due to
failure to split a zero-extended memory load. That particular pattern
is a bit special on the H8 in that it's split at assembly time primarily
to get the length computations correct. Arguably that alternative should
go away completely, but I haven't really looked into that.
Anyway, with the final-asm split we obviously need to match a define_split
somewhere. But none was ever written after adding CCZN optimizations. So
if we had a zero extend of a memory operand and it was used to eliminate
a compare, then we'd abort at final asm time.
Regression tested (in conjunction with various other in-progress patches) on
H8 without regressions.
gcc/
* config/h8300/extensions.md (CCZN setting zero extended load): Add
missing splitter.
@@ -47,6 +47,24 @@
operands[2] = gen_rtx_REG (QImode, REGNO (operands[0]));
})
+;; Similarly, but setting cczn.
+(define_split
+ [(set (reg:CCZN CC_REG)
+ (compare:CCZN
+ (zero_extend:HI (match_operand:QI 1 "general_operand_src" ""))
+ (const_int 0)))
+ (set (match_operand:HI 0 "register_operand" "")
+ (zero_extend:HI (match_dup 1)))]
+ "!REG_P (operands[1]) && reload_completed"
+ [(parallel [(set (match_dup 2) (match_dup 1))
+ (clobber (reg:CC CC_REG))])
+ (parallel [(set (reg:CCZN CC_REG)
+ (compare:CCZN (zero_extend:HI (match_dup 2)) (const_int 0)))
+ (set (match_dup 0) (zero_extend:HI (match_dup 2)))])]
+ {
+ operands[2] = gen_rtx_REG (QImode, REGNO (operands[0]));
+ })
+
(define_insn "*zero_extendqisi2"
[(set (match_operand:SI 0 "register_operand" "=r,r")
(zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]