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[2001:8b0:154:0:ea6a:64ff:fe24:f2fc]) by smtp.gmail.com with ESMTPSA id b18-20020adfde12000000b0020d0f111241sm24577303wrm.24.2022.06.09.06.36.08 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 09 Jun 2022 06:36:08 -0700 (PDT) Date: Thu, 9 Jun 2022 14:36:06 +0100 (BST) From: "Maciej W. Rozycki" To: gcc-patches@gcc.gnu.org Subject: [PATCH] RISC-V: Reset the length to the default of 4 for FP comparisons Message-ID: User-Agent: Alpine 2.20 (DEB 67 2015-01-07) MIME-Version: 1.0 X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Waterman , Kito Cheng Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" The default length for floating-point compare operations is overridden to 8, however the FEQ.fmt, FLT.fmt, FLE.fmt machine instructions and FGE.fmt, FGT.fmt assembly idioms the relevant RTL insns produce are all 4 bytes long each. And all the floating-point compare RTL insns that produce multiple machine instructions explicitly set their lengths. Remove the override then, letting the default of 4 apply for the single instruction case. gcc/ * config/riscv/riscv.md (length): Remove the explicit setting for "fcmp". --- Hi, So for: int feq (float x, float y) { return x == y; } we get: .globl feq .type feq, @function feq: feq.s a0,fa0,fa1 # 15 [c=4 l=8] *cstoresfdi4 ret # 24 [c=0 l=4] simple_return .size feq, .-feq which is obviously wrong given: Disassembly of section .text: 0000000000000000 : 0: a0b52553 feq.s a0,fa0,fa1 4: 8082 ret (hmm tabs are odd here too, but that's a binutils issue). I note that the override has always been there since the RISC-V port landed, so I take it it's a missed leftover from an earlier situation. With the change in place we instead get: .globl feq .type feq, @function feq: feq.s a0,fa0,fa1 # 15 [c=4 l=4] *cstoresfdi4 ret # 24 [c=0 l=4] simple_return .size feq, .-feq which I find so relieving. No regressions in the testsuite (and I haven't checked how it affects instruction scheduling, especially with `-Os', but I think it's obviously correct really). OK to apply? Maciej --- gcc/config/riscv/riscv.md | 2 -- 1 file changed, 2 deletions(-) gcc-riscv-fcmp-length.diff Index: gcc/gcc/config/riscv/riscv.md =================================================================== --- gcc.orig/gcc/config/riscv/riscv.md +++ gcc/gcc/config/riscv/riscv.md @@ -231,8 +231,6 @@ (eq_attr "got" "load") (const_int 8) - (eq_attr "type" "fcmp") (const_int 8) - ;; SHIFT_SHIFTs are decomposed into two separate instructions. (eq_attr "move_type" "shift_shift") (const_int 8)