From patchwork Fri Feb 4 18:44:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Maciej W. Rozycki" X-Patchwork-Id: 50808 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 4D0F13858436 for ; Fri, 4 Feb 2022 18:44:26 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-lf1-x12f.google.com (mail-lf1-x12f.google.com [IPv6:2a00:1450:4864:20::12f]) by sourceware.org (Postfix) with ESMTPS id 59D953858D28 for ; Fri, 4 Feb 2022 18:44:09 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 59D953858D28 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=embecosm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=embecosm.com Received: by mail-lf1-x12f.google.com with SMTP id b9so14351088lfq.6 for ; Fri, 04 Feb 2022 10:44:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=embecosm.com; s=google; h=date:from:to:cc:subject:message-id:user-agent:mime-version; bh=lK5ve6MvEr/kGJmODgxWlkRGuwZzWzkw6cW+yTFpbWQ=; b=N4Hy2xqYGlom26ENb7a8byrt4ME6bxvZQVDJblV4BYtyCS6F1DF6jg9WX9Cuo2rOGj esdyUgu1WdrsVP7F6TLeOmhEV0WnabrPArQnyTotXQFBdwt14uIRLVei3e6SLg3gns/1 g3zHF//L++AEO0fngqF3AUwefG4Mu2TOkDD1u2ym/tF7CwL3X9Ql0xO0VihhpawhCeal DU58Dnealfc4XbczkDhTfStX9F/nzT7MDvi1pEGwe46W5OIh570Xw7h95dXmrFtIm7AW wbjnpKOnHzk5Z8IU4jCmHP5waism0Ol4xjD5kr50gu7+lRjGjg/AoWF0hnJR0C/WeK2g YJhg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:user-agent :mime-version; bh=lK5ve6MvEr/kGJmODgxWlkRGuwZzWzkw6cW+yTFpbWQ=; b=P4KvZIZF5pMJY6UoCRZ4R89d6HwT0a8EGRYFcYKTPGE3y8AMENEvoi8G76EB4CCH6A u62XrPraFc6F687CG4P9MOB0VLWjUhNkU+2uQYTcY8zmhdzODbu7yNlOHHlPdVWtzbel 3dqCCZHacRKLJbfyqjnTJwLiP2HQ09ZQJbREgjBpFvYPZ+MdQdczZaEDeYBEqo6es6XB tqMjp3fkDUMzjBJJRPAf2qCnDLFgot0lCoai30qnZFdkd8nCKEHOGse1YUwbIKrJX5R3 MzeXfQ34DUOqpFo5stBfgsXUIj7Fr/NkPdsQvqZy2jEI0zfWi0olel2yHdk3gNhc1mRl luQw== X-Gm-Message-State: AOAM5305kvbWXoFNf5hlakVj+L8dOm6pEGpuKcRoVR2cwADP8tWBoOnI kt+eUQMCgAzf0zOZDS2V60MiOSaXwLUDtQ== X-Google-Smtp-Source: ABdhPJzMj4pyNqiez0tcBUEptFVXOjU/FijFPyd2k9ep0PODIGZmS++Jp/ZyIXjjQyIUgm4Hijag2w== X-Received: by 2002:a05:6512:68a:: with SMTP id t10mr202022lfe.520.1644000247936; Fri, 04 Feb 2022 10:44:07 -0800 (PST) Received: from [192.168.219.3] ([78.8.192.131]) by smtp.gmail.com with ESMTPSA id m17sm416932lfc.130.2022.02.04.10.44.06 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 04 Feb 2022 10:44:07 -0800 (PST) Date: Fri, 4 Feb 2022 18:44:04 +0000 (GMT) From: "Maciej W. Rozycki" To: gcc-patches@gcc.gnu.org Subject: [PATCH] doc: RISC-V: Document the `-misa-spec=' option Message-ID: User-Agent: Alpine 2.20 (DEB 67 2015-01-07) MIME-Version: 1.0 X-Spam-Status: No, score=-2.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, KAM_ASCII_DIVIDERS, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kito Cheng , Andrew Waterman Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" We have recently updated the default for the `-misa-spec=' option, yet we still have not documented it nor its `--with-isa-spec=' counterpart in the GCC manuals. Fix that. gcc/ * doc/install.texi (Configuration): Document `--with-isa-spec=' RISC-V option. * doc/invoke.texi (Option Summary): List `-misa-spec' RISC-V option. (RISC-V Options): Document it. --- Hi, Verified with `make info' and `make pdf'. OK to apply? Maciej --- gcc/doc/install.texi | 14 ++++++++++++++ gcc/doc/invoke.texi | 16 ++++++++++++++++ 2 files changed, 30 insertions(+) gcc-riscv-misa-doc.diff Index: gcc/gcc/doc/install.texi =================================================================== --- gcc.orig/gcc/doc/install.texi +++ gcc/gcc/doc/install.texi @@ -1599,6 +1599,20 @@ On certain targets this option sets the size as a power of two in bytes. On AArch64 @var{size} is required to be either 12 (4KB) or 16 (64KB). +@item --with-isa-spec=@var{ISA-spec-string} +On RISC-V targets specify the default version of the RISC-V ISA specification +to produce code conforming to. The possibilities for @var{ISA-spec-string} +are: +@table @code +@item 2.2 +Produce code conforming to version 2.2. +@item 20190608 +Produce code conforming to version 20190608. +@item 20191213 +Produce code conforming to version 20191213. +@end table +In the absence of this configuration option the default version is 20191213. + @item --enable-__cxa_atexit Define if you want to use __cxa_atexit, rather than atexit, to register C++ destructors for local statics and global objects. Index: gcc/gcc/doc/invoke.texi =================================================================== --- gcc.orig/gcc/doc/invoke.texi +++ gcc/gcc/doc/invoke.texi @@ -1184,6 +1184,7 @@ See RS/6000 and PowerPC Options. -mabi=@var{ABI-string} @gol -mfdiv -mno-fdiv @gol -mdiv -mno-div @gol +-misa-spec=@var{ISA-spec-string} @gol -march=@var{ISA-string} @gol -mtune=@var{processor-string} @gol -mpreferred-stack-boundary=@var{num} @gol @@ -27632,6 +27633,21 @@ Do or don't use hardware instructions fo M extension. The default is to use them if the specified architecture has these instructions. +@item -misa-spec=@var{ISA-spec-string} +@opindex misa-spec +Specify the version of the RISC-V ISA specification to produce code conforming +to. The possibilities for @var{ISA-spec-string} are: +@table @code +@item 2.2 +Produce code conforming to version 2.2. +@item 20190608 +Produce code conforming to version 20190608. +@item 20191213 +Produce code conforming to version 20191213. +@end table +The default is @option{-misa-spec=20191213} unless GCC has been configured +with @option{--with-isa-spec=} specifying a different default version. + @item -march=@var{ISA-string} @opindex march Generate code for given RISC-V ISA (e.g.@: @samp{rv64im}). ISA strings must be