From patchwork Thu Jan 20 15:44:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Maciej W. Rozycki" X-Patchwork-Id: 50282 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A14543857405 for ; Thu, 20 Jan 2022 15:44:46 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by sourceware.org (Postfix) with ESMTPS id 3343A3858D37 for ; Thu, 20 Jan 2022 15:44:30 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 3343A3858D37 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=embecosm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=embecosm.com Received: by mail-lf1-x12e.google.com with SMTP id m3so23435707lfu.0 for ; Thu, 20 Jan 2022 07:44:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=embecosm.com; s=google; h=date:from:to:cc:subject:message-id:user-agent:mime-version; bh=lWpEE5W+F3MqUe3AzjXu2GagaMWzReO8yPZCd1/JnOk=; b=ZG9o782SBKJbE3ogJkuzDX1Lj+GoyhBDVlD4xHLaG3X1PG5VjYNft1dqJGAE+yOuK/ 2z1gXPDRVV9FbHjxTznbLUu+JRh4nlUxiixY+82sax1WKAqqJhUD2zsWBkHn7enxlh/T kwnliyUVUQCh+YI+w4qiNkDP36HgEErvqT//9YrvtulT/moWAzHpUqfFxgIr2DTnvZfG 8uJTh7gjsZaFkw3+UuWDIlJ64KKgS45vaa/5UWrV/offw8EYdXCfzUpbrROM+o/UG6pN m+GHN4T3jS+CwG7BxwrGUHKLUmKok9PvC/73n/b8XKC8ZyzXv/xZhoxQsfzWK3ksW0HG F5jg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:user-agent :mime-version; bh=lWpEE5W+F3MqUe3AzjXu2GagaMWzReO8yPZCd1/JnOk=; b=FN9kP+hx8IFthcXFFUbhrLOSyHcHKvTOjhhIx4n4teFdRlsvEPOD/iY6g14U4tBrgx 01ZyGPb3AaYZksY9ZAbkOxaomtjGAYUDXArLcPVhwy5d5VL7dNwU2jpcPLw697OkhOq+ BtnedyetQT5E1WjxouAPC4GKDFjxPmIuTs66fIMzy3lbaeln+yMiFnM7TtVYt46gibmh mLPFkgrCeyvTmOosi0m1GPquCxceByV4SGBw45mEr0YHyuiX08ElTZbnfoHGeU1QqmDX /5oGFQt8qtKzawVn3ZXPAj0AKs+th7B2BcQ5HCHRJvA9lxhPuLczR6vH+DsM8xEG5r2i a35Q== X-Gm-Message-State: AOAM533h3yyX6dg4rez8DetLqIniNw+QJFg8n3NL5Y4YMGHGUV3JkDW2 2JIUrx3uBsZ0hauO9qgMHi95ng2IPcZCD3Rh X-Google-Smtp-Source: ABdhPJxnNg7KFH+6QvkVW2gWBj8bWEAQdy49izugxYSQSUueizmvJFCZ6iNWHFsRO7awuPKxGCkhJw== X-Received: by 2002:a05:651c:a0f:: with SMTP id k15mr12064797ljq.451.1642693468776; Thu, 20 Jan 2022 07:44:28 -0800 (PST) Received: from [192.168.219.3] ([78.8.192.131]) by smtp.gmail.com with ESMTPSA id q3sm394431lfc.81.2022.01.20.07.44.27 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 20 Jan 2022 07:44:28 -0800 (PST) Date: Thu, 20 Jan 2022 15:44:25 +0000 (GMT) From: "Maciej W. Rozycki" To: gcc-patches@gcc.gnu.org Subject: [PATCH][GCC13?] RISC-V: Replace `smin'/`smax' RTL patterns with `fmin'/`fmax' Message-ID: User-Agent: Alpine 2.20 (DEB 67 2015-01-07) MIME-Version: 1.0 X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kito Cheng , Andrew Waterman Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" RISC-V FMIN and FMAX machine instructions are IEEE-754-conformant[1]: "For FMIN and FMAX, if at least one input is a signaling NaN, or if both inputs are quiet NaNs, the result is the canonical NaN. If one operand is a quiet NaN and the other is not a NaN, the result is the non-NaN operand." as required by our `fminM3' and `fmaxM3' standard RTL patterns. However we only define `sminM3' and `smaxM3' standard RTL patterns to produce the FMIN and FMAX machine instructions, which in turn causes the `__builtin_fmin' and `__builtin_fmax' family of intrinsics to emit the corresponding libcalls rather than the relevant machine instructions. Rename the `smin3' and `smax3' patterns to `fmin3' and `fmax3' respectively then, removing the need to use libcalls for IEEE 754 semantics with the minimum and maximum operations. [1] "The RISC-V Instruction Set Manual, Volume I: User-Level ISA", Document Version 2.2, May 7, 2017, Section 8.3 "NaN Generation and Propagation", p. 48 gcc/ * config/riscv/riscv.md (smin3): Rename pattern to... (fmin3): ... this. (smax3): Likewise... (fmax3): ... this. Acked-by: Palmer Dabbelt # for 13 --- Hi, It's not clear to me how it's been missed or whether there is anything I might be actually missing. It looks to me like a clear oversight however. And in any case this change has passed full GCC regression testing (except for the D frontend, which has stopped being built recently due to a defect in Debian I haven't yet got to getting fixed) with the `riscv64-linux-gnu' target using the HiFive Unmatched (U74 CPU) target board, so it seems to be doing the right thing. Timing might a bit unfortunate for this submission and given that it is not a regression fix I guess this is GCC 13 material. Please let me know otherwise. In any case OK to apply (when the time comes)? Maciej --- gcc/config/riscv/riscv.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) gcc-riscv-fmin-fmax.diff Index: gcc/gcc/config/riscv/riscv.md =================================================================== --- gcc.orig/gcc/config/riscv/riscv.md +++ gcc/gcc/config/riscv/riscv.md @@ -1214,7 +1214,7 @@ ;; ;; .................... -(define_insn "smin3" +(define_insn "fmin3" [(set (match_operand:ANYF 0 "register_operand" "=f") (smin:ANYF (match_operand:ANYF 1 "register_operand" " f") (match_operand:ANYF 2 "register_operand" " f")))] @@ -1223,7 +1223,7 @@ [(set_attr "type" "fmove") (set_attr "mode" "")]) -(define_insn "smax3" +(define_insn "fmax3" [(set (match_operand:ANYF 0 "register_operand" "=f") (smax:ANYF (match_operand:ANYF 1 "register_operand" " f") (match_operand:ANYF 2 "register_operand" " f")))]