diff mbox series

[committed] Fix testsuite expectations for RVV after recent change

Message ID af403eb4-4ba2-4b02-a0f6-12d4f985abd3@ventanamicro.com
State New
Headers
Series [committed] Fix testsuite expectations for RVV after recent change |

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Commit Message

Jeff Law Jan. 7, 2025, 9:29 p.m. UTC 
  Tamar's recent improvement to improve affine unsigned folding for 
exchange2 twiddle code generation for a couple tests in the RVV 
testsuite just enough to cause testsuite failures.

I've looked at both tests before/after Tamar's change and the code is 
clearly better -- essentially tighter vector loops due to improvements 
in address arithmetic.  Additionally we have fewer vsetvls after Tamar's 
patch.

Given that I'm just making the obvious adjustments to the expected 
assembly and pushing to the trunk.

Jeff
commit c6b5398e9e3c387910e1736f06525a0724a84b3e
Author: Jeff Law <jlaw@ventanamicro.com>
Date:   Tue Jan 7 14:27:28 2025 -0700

    Fix testsuite expectations for RVV after recent change
    
    Tamar's recent improvement to improve affine unsigned folding for exchange2
    twiddle code generation for a couple tests in the RVV testsuite just enough to
    cause testsuite failures.
    
    I've looked at both tests before/after Tamar's change and the code is clearly
    better -- essentially tighter vector loops due to improvements in address
    arithmetic.  Additionally we have fewer vsetvls after Tamar's patch.
    
    Given that I'm just making the obvious adjustments to the expected assembly and
    pushing to the trunk.
    
    gcc/testsuite
            * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-3.c: Update expected
            output.
            * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-12.c: Likewise.
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-12.c
index b96f2671f99..5cecb453d72 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-12.c
@@ -35,4 +35,4 @@  void f2 (int32_t * restrict in, int32_t * restrict in2, int32_t * restrict out,
     }
 }
 
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-3.c
index 2c8d3671c0e..795611e53da 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-3.c
@@ -26,5 +26,5 @@  void f2 (int32_t * restrict in, int32_t * restrict in2, int32_t * restrict out,
     }
 }
 
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */