From patchwork Fri Mar 3 04:53:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Michael Collison X-Patchwork-Id: 65952 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 6C10C384B04E for ; Fri, 3 Mar 2023 04:53:34 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-qt1-x82b.google.com (mail-qt1-x82b.google.com [IPv6:2607:f8b0:4864:20::82b]) by sourceware.org (Postfix) with ESMTPS id 15133384F00C for ; Fri, 3 Mar 2023 04:53:16 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 15133384F00C Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-qt1-x82b.google.com with SMTP id cf14so1705384qtb.10 for ; Thu, 02 Mar 2023 20:53:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:content-language:to:subject:from :user-agent:mime-version:date:message-id:from:to:cc:subject:date :message-id:reply-to; bh=FPO0X5Bjn0SaOLebzQFeV7JmnGyXqX24tQrz8/6R4jw=; b=CLjRyqKD0VRqNPb0auGmNIrMuPlHjwi1t6FDYbF/CTSYulSSzQe0K6NXrdO6sWOsG3 4u45bAEDMpwLN/5XuB0ywjNIlGhk+WxEPYnQS5Wlii3MGFgOE871KT32UNkTJk/sAzDS pCvlJxcflYC8ghvTSXbzlFTY90hPOXMzf9KQL8WEQglCc0iVF6hwZGFb+4eMApvLl3M2 tdVQek95msg7d1BTN74iVFAwtUIZoRm/vMOHPMQjSDoyHLKgwpj4sNRMXkCE5h3j66SW Jj9V98OqRan4awuc/5LN3ag2GEn7ECsTKPdUeXgUzHm7Boo+TmNjpnSpg3MpYvJE6DGO sQHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:content-language:to:subject:from :user-agent:mime-version:date:message-id:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=FPO0X5Bjn0SaOLebzQFeV7JmnGyXqX24tQrz8/6R4jw=; b=V2uKi/wMukjrqI6+/qlOW3SBjcaYlMru8l1+sQ9qTUZNBvM/1mKdoBvgb+gid3I2YO +Ne4XmAqJhNW9Gumt/1dHLXfyB+oZaIB3nszP0DUda/a+vTSB2R1UEoEuQfIv7lTdlAg 8K7VHRAh6LR/eEdQKHH4NzWzjc7BPDr0+1As20zDY0l0K+9Hiwxir4jclPno+XHnqdjr zs0qZINZS24L3rcuLjiJiJE93fgewhxGBggw4KPyLCuogHxSPpf4XBAkxUeE6YQbyBjj tHLJNIwPmxtLHhWDC49rtivL53XO5X597XPRhmfdk2pE6/doyNS3WGzUdorPV95l+qYr HBZg== X-Gm-Message-State: AO0yUKVv4zQL0huPdX2AdJ+b6dFrIB4f2e2RpTh+tzJmnBLFedc5c3Gh 6x6+eQrzjL60itSbD8mRklp8ER7ppoP0TqHb X-Google-Smtp-Source: AK7set89Bz3gk+Cr2THV3XB5rGikBjNTC5hL9CuJD7vWo94SMj9NCg/eWMrWpUFE7ViwZotXrprl3g== X-Received: by 2002:ac8:5882:0:b0:3b9:b761:b0aa with SMTP id t2-20020ac85882000000b003b9b761b0aamr979913qta.11.1677819195197; Thu, 02 Mar 2023 20:53:15 -0800 (PST) Received: from [192.168.86.117] ([136.57.172.92]) by smtp.gmail.com with ESMTPSA id bl14-20020a05620a1a8e00b00706bc44fda8sm1002653qkb.79.2023.03.02.20.53.14 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 02 Mar 2023 20:53:14 -0800 (PST) Message-ID: Date: Thu, 2 Mar 2023 23:53:14 -0500 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.7.1 From: Michael Collison Subject: [PATCH 04/07] RISC-V: Add auto-vectorization support To: gcc-patches Content-Language: en-US X-Spam-Status: No, score=-10.8 required=5.0 tests=BAYES_00, BODY_8BITS, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" This patch adds support for functions used in implementing various portions of autovectorization support. gcc/ChangeLog:     * config/riscv/riscv-v.cc (riscv_classify_vlmul_field):     New function.     (riscv_vector_preferred_simd_mode): Ditto.     (get_mask_policy_no_pred): Ditto.     (get_tail_policy_no_pred): Ditto.     (riscv_tuple_mode_p): Ditto.     (riscv_classify_nf): Ditto.     (riscv_vlmul_regsize): Ditto.     (riscv_vector_mask_mode_p): Ditto.     (riscv_vector_get_mask_mode): Ditto. ---  gcc/config/riscv/riscv-v.cc | 176 ++++++++++++++++++++++++++++++++++++  1 file changed, 176 insertions(+)  { @@ -162,6 +199,64 @@ calculate_ratio (unsigned int sew, enum vlmul_type vlmul)    return ratio;  } +/* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE for RVV.  */ + +machine_mode +riscv_vector_preferred_simd_mode (scalar_mode mode, unsigned vf) +{ +  if (!TARGET_VECTOR) +    return word_mode; + +  switch (mode) +    { +    case E_QImode: +      return vf == 1   ? VNx8QImode +         : vf == 2 ? VNx16QImode +         : vf == 4 ? VNx32QImode +               : VNx64QImode; +      break; +    case E_HImode: +      return vf == 1   ? VNx4HImode +         : vf == 2 ? VNx8HImode +         : vf == 4 ? VNx16HImode +               : VNx32HImode; +      break; +    case E_SImode: +      return vf == 1   ? VNx2SImode +         : vf == 2 ? VNx4SImode +         : vf == 4 ? VNx8SImode +               : VNx16SImode; +      break; +    case E_DImode: +      if (riscv_vector_elen_flags != MASK_VECTOR_ELEN_32 +      && riscv_vector_elen_flags != MASK_VECTOR_ELEN_FP_32) +    return vf == 1     ? VNx1DImode +           : vf == 2 ? VNx2DImode +           : vf == 4 ? VNx4DImode +             : VNx8DImode; +      break; +    case E_SFmode: +      if (TARGET_HARD_FLOAT && riscv_vector_elen_flags != MASK_VECTOR_ELEN_32 +      && riscv_vector_elen_flags != MASK_VECTOR_ELEN_64) +    return vf == 1     ? VNx2SFmode +           : vf == 2 ? VNx4SFmode +           : vf == 4 ? VNx8SFmode +             : VNx16SFmode; +      break; +    case E_DFmode: +      if (TARGET_DOUBLE_FLOAT && TARGET_VECTOR_ELEN_FP_64) +    return vf == 1     ? VNx1DFmode +           : vf == 2 ? VNx2DFmode +           : vf == 4 ? VNx4DFmode +             : VNx8DFmode; +      break; +    default: +      break; +    } + +  return word_mode; +} +  /* Emit an RVV unmask && vl mov from SRC to DEST.  */  static void  emit_pred_op (unsigned icode, rtx mask, rtx dest, rtx src, rtx len, @@ -374,6 +469,87 @@ get_avl_type_rtx (enum avl_type type)    return gen_int_mode (type, Pmode);  } +rtx +get_mask_policy_no_pred () +{ +  return get_mask_policy_for_pred(PRED_TYPE_none); +} + +rtx +get_tail_policy_no_pred () +{ +  return get_mask_policy_for_pred(PRED_TYPE_none); +} + +/* Return true if it is a RVV tuple mode. */ +bool +riscv_tuple_mode_p (machine_mode mode ATTRIBUTE_UNUSED) +{ +  return false; +} + +/* Return nf for a machine mode. */ +int +riscv_classify_nf (machine_mode mode) +{ +  switch (mode) +    { + +    default: +      break; +    } + +  return 1; +} + +/* Return vlmul register size for a machine mode. */ +int +riscv_vlmul_regsize (machine_mode mode) +{ +  if (GET_MODE_CLASS (mode) == MODE_VECTOR_BOOL) +    return 1; +  switch (riscv_classify_vlmul_field (mode)) +    { +    case VLMUL_FIELD_001: +      return 2; +    case VLMUL_FIELD_010: +      return 4; +    case VLMUL_FIELD_011: +      return 8; +    case VLMUL_FIELD_100: +      gcc_unreachable (); +    default: +      return 1; +    } +} + +/* Return true if it is a RVV mask mode. */ +bool +riscv_vector_mask_mode_p (machine_mode mode) +{ +  return (mode == VNx1BImode || mode == VNx2BImode || mode == VNx4BImode +      || mode == VNx8BImode || mode == VNx16BImode || mode == VNx32BImode +      || mode == VNx64BImode); +} + +/* Implement TARGET_VECTORIZE_GET_MASK_MODE for RVV.  */ + +opt_machine_mode +riscv_vector_get_mask_mode (machine_mode mode) +{ +  machine_mode mask_mode; +  int nf = 1; +  if (riscv_tuple_mode_p (mode)) +    nf = riscv_classify_nf (mode); + +  FOR_EACH_MODE_IN_CLASS (mask_mode, MODE_VECTOR_BOOL) +  if (GET_MODE_INNER (mask_mode) == BImode +      && known_eq (GET_MODE_NUNITS (mask_mode) * nf, GET_MODE_NUNITS (mode)) +      && riscv_vector_mask_mode_p (mask_mode)) +    return mask_mode; +  return default_get_mask_mode (mode); +} +  /* Return the RVV vector mode that has NUNITS elements of mode INNER_MODE.     This function is not only used by builtins, but also will be used by     auto-vectorization in the future.  */ diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 58007cc16eb..58f69e259c0 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -39,9 +39,11 @@  #include "emit-rtl.h"  #include "tm_p.h"  #include "target.h" +#include "targhooks.h"  #include "expr.h"  #include "optabs.h"  #include "tm-constrs.h" +#include "riscv-vector-builtins.h"  using namespace riscv_vector; @@ -108,6 +110,41 @@ const_vec_all_same_in_range_p (rtx x, HOST_WIDE_INT minval,        && IN_RANGE (INTVAL (elt), minval, maxval));  } +/* Return the vlmul field for a specific machine mode. */ +unsigned int +riscv_classify_vlmul_field (enum machine_mode mode) +{ +  /* Make the decision based on the mode's enum value rather than its +     properties, so that we keep the correct classification regardless +     of -mriscv-vector-bits.  */ +  switch (mode) +    { +    case E_VNx8BImode: +      return VLMUL_FIELD_111; + +    case E_VNx4BImode: +      return VLMUL_FIELD_110; + +    case E_VNx2BImode: +      return VLMUL_FIELD_101; + +    case E_VNx16BImode: +      return VLMUL_FIELD_000; + +    case E_VNx32BImode: +      return VLMUL_FIELD_001; + +    case E_VNx64BImode: +      return VLMUL_FIELD_010; + +    default: +      break; +    } + +  /* we don't care about VLMUL for Mask */ +  return VLMUL_FIELD_000; +} +  rtx  emit_vlmax_vsetvl (machine_mode vmode)