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(175.177.45.176 with ) by smtp5008.mail.kks.ynwp.yahoo.co.jp with SMTP; 18 Jul 2022 12:47:57 -0000 X-YMail-JAS: eLFdfxkVM1kGiQSKNQ7c1_BvteaIHl_HvwzTniLjJjBR51TEbday8dW20jR0a_ZukIciqjUb885_09HgN.xcmkyENVCZ6pAQIbXuwLNR8zUuaOXSu8S3nenKAuxyCdwduw.21w.6GA-- X-Apparently-From: X-YMail-OSG: X0wxItUVM1m3rVcJKnM4HQcflxbuYi9v0J3UzrZ5cmN_RgD bVJ5UspdMyDlySxjeshhRZ4Ik6pr8oLrMBxFC1V.lE.QKgB1GMODa_J2ixDb FtwGav25zkUQ4pq7_5c4RAmjjvK07yzLRm69WtnqSBFDCY0VEecq4ac1fTMi oh8m8lYObn2Y2sFnpJQvB_zniTvtnDlvCwkGpWQiBICMquLZ.zP2UYl3LUlv scoqIItyEZryIlbuU7TYoBT5izu9XAxcmrUnZ.jCpsw40UIuQd5ANrWI0OFC jLw.3_kEzScSAgBLCqVjc69X7ElB9FcFepuFVXrhvyGUjtOV.mtxAML7Fknf Z4uuZ.vO56I_dge8SdhwnQfaW7ojYXBzBNed17vGTA6Xjkug8asnp1cgzE.U uQkL2fLzPkVHkSqAu2h..Omt8.3WR9gmVL4HYQohQxXW2MPBJuDHRTWENX1n HdXsCv24IbkYGG4Sh_xVuJ832fz0EIp.98md5ym3P2SgUeJJQ_rfCWduuo.h K03_AOjgabJVLY6xPlP0LtLYnyPxfjEzxghK0BOFpbwhpuGyo1MCEg2akwWz OdBWWsCM8tAqNnELfl3.pfateHLhRst_o9qjHcZOLl70yhD30KX4ofE34SgU zuo.KPXVif30beVCb4i7hgyQIbnJN5Z9bLhaf2qadInXA6dGflGR.7WlXJxd DUbBx9TvigfYaMe_7PMOX5wtNhqvSOv2UGYBJneNEgsrF_u.38PW4IlHZh7A GAdhIDYCHVg.44jUrByTIl3xwrr2R5sMekiZNzMBt7OaT57vhZ1GEkyulBMh eK2AQ0S8pCnJ0oYaMNWGIgpesvv7iY8vLGco8Dg1zLDWwN9BuT4eMo6JjQv5 pBbRs_LR4LYopFSq5MclvH4vDbvEKbn5Xa9n3d.DAYD.0aFklcSNwke_KdFq ELyuZErLvStBZHE9Kow-- Message-ID: Date: Mon, 18 Jul 2022 21:43:45 +0900 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 6.1; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.0.2 Content-Language: en-US To: GCC Patches Subject: [PATCH] xtensa: Correct the relative RTX cost that corresponds to the Move Immediate "MOVI" instruction X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Takayuki 'January June' Suwa via Gcc-patches From: Takayuki 'January June' Suwa Reply-To: Takayuki 'January June' Suwa Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" This patch corrects the overestimation of the relative cost of '(set (reg) (const_int N))' where N fits into the instruction itself. In fact, such overestimation confuses the RTL loop invariant motion pass. As a result, it brings almost no negative impact from the speed point of view, but addtiional reg-reg move instructions and register allocation pressure about the size. /* example, optimized for size */ extern int foo(void); extern int array[16]; void test_0(void) { unsigned int i; for (i = 0; i < sizeof(array)/sizeof(*array); ++i) array[i] = 1024; } void test_1(void) { unsigned int i; for (i = 0; i < sizeof(array)/sizeof(*array); ++i) array[i] = array[i] ? 1024 : 0; } void test_2(void) { unsigned int i; for (i = 0; i < sizeof(array)/sizeof(*array); ++i) array[i] = foo() ? 0 : 1024; } ;; before .literal_position .literal .LC0, array test_0: l32r a3, .LC0 movi.n a2, 0 movi a4, 0x400 // OK .L2: s32i.n a4, a3, 0 addi.n a2, a2, 1 addi.n a3, a3, 4 bnei a2, 16, .L2 ret.n .literal_position .literal .LC1, array test_1: l32r a2, .LC1 movi.n a3, 0 movi a5, 0x400 // NG .L6: l32i.n a4, a2, 0 beqz.n a4, .L5 mov.n a4, a5 // should be "movi a4, 0x400" .L5: s32i.n a4, a2, 0 addi.n a3, a3, 1 addi.n a2, a2, 4 bnei a3, 16, .L6 ret.n .literal_position .literal .LC2, array test_2: addi sp, sp, -32 s32i.n a12, sp, 24 l32r a12, .LC2 s32i.n a13, sp, 20 s32i.n a14, sp, 16 s32i.n a15, sp, 12 s32i.n a0, sp, 28 addi a13, a12, 64 movi.n a15, 0 // NG movi a14, 0x400 // and wastes callee-saved registers (only 4) .L11: call0 foo mov.n a3, a14 // should be "movi a3, 0x400" movnez a3, a15, a2 s32i.n a3, a12, 0 addi.n a12, a12, 4 bne a12, a13, .L11 l32i.n a0, sp, 28 l32i.n a12, sp, 24 l32i.n a13, sp, 20 l32i.n a14, sp, 16 l32i.n a15, sp, 12 addi sp, sp, 32 ret.n ;; after .literal_position .literal .LC0, array test_0: l32r a3, .LC0 movi.n a2, 0 movi a4, 0x400 // OK .L2: s32i.n a4, a3, 0 addi.n a2, a2, 1 addi.n a3, a3, 4 bnei a2, 16, .L2 ret.n .literal_position .literal .LC1, array test_1: l32r a2, .LC1 movi.n a3, 0 .L6: l32i.n a4, a2, 0 beqz.n a4, .L5 movi a4, 0x400 // OK .L5: s32i.n a4, a2, 0 addi.n a3, a3, 1 addi.n a2, a2, 4 bnei a3, 16, .L6 ret.n .literal_position .literal .LC2, array test_2: addi sp, sp, -16 s32i.n a12, sp, 8 l32r a12, .LC2 s32i.n a13, sp, 4 s32i.n a0, sp, 12 addi a13, a12, 64 .L11: call0 foo movi.n a3, 0 // OK movi a4, 0x400 // and less register allocation pressure moveqz a3, a4, a2 s32i.n a3, a12, 0 addi.n a12, a12, 4 bne a12, a13, .L11 l32i.n a0, sp, 12 l32i.n a12, sp, 8 l32i.n a13, sp, 4 addi sp, sp, 16 ret.n gcc/ChangeLog: * config/xtensa/xtensa.cc (xtensa_rtx_costs): Change the relative cost of '(set (reg) (const_int N))' where N fits into signed 12-bit from 4 to 0 if optimizing for size. And use the appropriate macro instead of the bare number 4. --- gcc/config/xtensa/xtensa.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/config/xtensa/xtensa.cc b/gcc/config/xtensa/xtensa.cc index 94337452ba8..a851a7ae6b3 100644 --- a/gcc/config/xtensa/xtensa.cc +++ b/gcc/config/xtensa/xtensa.cc @@ -4073,7 +4073,7 @@ xtensa_rtx_costs (rtx x, machine_mode mode, int outer_code, case SET: if (xtensa_simm12b (INTVAL (x))) { - *total = 4; + *total = speed ? COSTS_N_INSNS (1) : 0; return true; } break;