From patchwork Fri Oct 15 15:13:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John David Anglin X-Patchwork-Id: 46280 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id B2C94385781F for ; Fri, 15 Oct 2021 15:13:42 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from cmx-torrgo002.bell.net (mta-tor-001.bell.net [209.71.212.28]) by sourceware.org (Postfix) with ESMTP id 5F09C385842E for ; Fri, 15 Oct 2021 15:13:24 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 5F09C385842E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=bell.net Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=bell.net X-RG-CM-BuS: 0 X-RG-CM-SC: 0 X-RG-CM: Clean X-Originating-IP: [67.71.8.137] X-RG-Env-Sender: dave.anglin@bell.net X-RG-Rigid: 60C8802C0828E5D3 X-CM-Envelope: MS4xfIdLehfh7vYwzwS9wqIFs8j2oyPz/q9zlbB8iv+hgg5zMg22NkyTFI31Cg7O8Hmgb7dB5zlTrdcUox3sLCwchafo8UU4zLUbB+RY5TcfXzzhfeyK9L62 ubRyx6es6u4M8kyrPB2JfHeapJWJJv4WbsL4c+aNXvhSkGw1YlgCKIDz7QlqSrlRIVPe0w0+TsQ24zUagL9HWvCte7W82UAn6b6nxPKk4/iparq4w+KmT9vC JrawAOC+l2fiGx5YHsU2Zw== X-CM-Analysis: v=2.4 cv=Zd5+iuZA c=1 sm=1 tr=0 ts=61699a93 a=jrdA9tB8yuRqUzQ1EpSZjA==:117 a=jrdA9tB8yuRqUzQ1EpSZjA==:17 a=IkcTkHD0fZMA:10 a=mDV3o1hIAAAA:8 a=SFU7Vnvo0sLH3pJrsuIA:9 a=QEXdDO2ut3YA:10 a=_FVE-zBwftR9WsbkzFJk:22 Received: from [192.168.2.49] (67.71.8.137) by cmx-torrgo002.bell.net (5.8.716.03) (authenticated as dave.anglin@bell.net) id 60C8802C0828E5D3; Fri, 15 Oct 2021 11:13:23 -0400 Message-ID: Date: Fri, 15 Oct 2021 11:13:23 -0400 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.2.0 Content-Language: en-US To: GCC Patches From: John David Anglin Subject: [committed] hppa: Consistently use "rG" constraint for copy instruction in move patterns X-Spam-Status: No, score=-8.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SCC_5_SHORT_WORD_LINES, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Some move patterns on hppa use the "rG" constraint and some just use the "r" constraint for the copy instruction. This patch makes all the move patterns consistent. It causes a copy of register %r0 to always be used to zero a register. There's no functional change since there are multiple ways to zero integer registers. Tested on hppa2.0w-hp-hpux11.11 and hppa64-hp-hpux11.11. Committed to active branches. Dave --- Consistently use "rG" constraint for copy instruction in move patterns 2021-10-15 John David Anglin gcc/ChangeLog: * config/pa/pa.md: Consistently use "rG" constraint for copy instruction in move patterns. diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md index 13a25381b6d..5cda3b79933 100644 --- a/gcc/config/pa/pa.md +++ b/gcc/config/pa/pa.md @@ -2186,14 +2186,14 @@ [(set (match_operand:SI 0 "move_dest_operand" "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T,?r,?*f") (match_operand:SI 1 "move_src_operand" - "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f,*f,r"))] + "A,rG,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f,*f,r"))] "(register_operand (operands[0], SImode) || reg_or_0_operand (operands[1], SImode)) && !TARGET_SOFT_FLOAT && !TARGET_64BIT" "@ ldw RT'%A1,%0 - copy %1,%0 + copy %r1,%0 ldi %1,%0 ldil L'%1,%0 {zdepi|depwi,z} %Z1,%0 @@ -2214,14 +2214,14 @@ [(set (match_operand:SI 0 "move_dest_operand" "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T") (match_operand:SI 1 "move_src_operand" - "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f"))] + "A,rG,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f"))] "(register_operand (operands[0], SImode) || reg_or_0_operand (operands[1], SImode)) && !TARGET_SOFT_FLOAT && TARGET_64BIT" "@ ldw RT'%A1,%0 - copy %1,%0 + copy %r1,%0 ldi %1,%0 ldil L'%1,%0 {zdepi|depwi,z} %Z1,%0 @@ -2240,14 +2240,14 @@ [(set (match_operand:SI 0 "move_dest_operand" "=r,r,r,r,r,r,Q,!*q,!r") (match_operand:SI 1 "move_src_operand" - "A,r,J,N,K,RQ,rM,!rM,!*q"))] + "A,rG,J,N,K,RQ,rM,!rM,!*q"))] "(register_operand (operands[0], SImode) || reg_or_0_operand (operands[1], SImode)) && TARGET_SOFT_FLOAT && TARGET_64BIT" "@ ldw RT'%A1,%0 - copy %1,%0 + copy %r1,%0 ldi %1,%0 ldil L'%1,%0 {zdepi|depwi,z} %Z1,%0 @@ -2381,13 +2381,13 @@ [(set (match_operand:SI 0 "move_dest_operand" "=r,r,r,r,r,r,Q,!*q,!r") (match_operand:SI 1 "move_src_operand" - "A,r,J,N,K,RQ,rM,!rM,!*q"))] + "A,rG,J,N,K,RQ,rM,!rM,!*q"))] "(register_operand (operands[0], SImode) || reg_or_0_operand (operands[1], SImode)) && TARGET_SOFT_FLOAT" "@ ldw RT'%A1,%0 - copy %1,%0 + copy %r1,%0 ldi %1,%0 ldil L'%1,%0 {zdepi|depwi,z} %Z1,%0 @@ -2909,11 +2909,11 @@ [(set (match_operand:HI 0 "move_dest_operand" "=r,r,r,r,r,Q,!*q,!r") (match_operand:HI 1 "move_src_operand" - "r,J,N,K,RQ,rM,!rM,!*q"))] + "rG,J,N,K,RQ,rM,!rM,!*q"))] "(register_operand (operands[0], HImode) || reg_or_0_operand (operands[1], HImode))" "@ - copy %1,%0 + copy %r1,%0 ldi %1,%0 ldil L'%1,%0 {zdepi|depwi,z} %Z1,%0 @@ -3069,11 +3069,11 @@ [(set (match_operand:QI 0 "move_dest_operand" "=r,r,r,r,r,Q,!*q,!r") (match_operand:QI 1 "move_src_operand" - "r,J,N,K,RQ,rM,!rM,!*q"))] + "rG,J,N,K,RQ,rM,!rM,!*q"))] "(register_operand (operands[0], QImode) || reg_or_0_operand (operands[1], QImode))" "@ - copy %1,%0 + copy %r1,%0 ldi %1,%0 ldil L'%1,%0 {zdepi|depwi,z} %Z1,%0 @@ -4047,12 +4047,12 @@ [(set (match_operand:DF 0 "move_dest_operand" "=!*r,*r,*r,*r,*r,Q,f,f,T") (match_operand:DF 1 "move_src_operand" - "!*r,J,N,K,RQ,*rG,fG,RT,f"))] + "!*rG,J,N,K,RQ,*rG,fG,RT,f"))] "(register_operand (operands[0], DFmode) || reg_or_0_operand (operands[1], DFmode)) && !TARGET_SOFT_FLOAT && TARGET_64BIT" "@ - copy %1,%0 + copy %r1,%0 ldi %1,%0 ldil L'%1,%0 depdi,z %z1,%0 @@ -4069,12 +4069,12 @@ [(set (match_operand:DF 0 "move_dest_operand" "=!*r,*r,*r,*r,*r,Q") (match_operand:DF 1 "move_src_operand" - "!*r,J,N,K,RQ,*rG"))] + "!*rG,J,N,K,RQ,*rG"))] "(register_operand (operands[0], DFmode) || reg_or_0_operand (operands[1], DFmode)) && TARGET_SOFT_FLOAT && TARGET_64BIT" "@ - copy %1,%0 + copy %r1,%0 ldi %1,%0 ldil L'%1,%0 depdi,z %z1,%0 @@ -4221,13 +4221,13 @@ [(set (match_operand:DI 0 "move_dest_operand" "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T") (match_operand:DI 1 "move_src_operand" - "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f"))] + "A,rG,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f"))] "(register_operand (operands[0], DImode) || reg_or_0_operand (operands[1], DImode)) && !TARGET_SOFT_FLOAT && TARGET_64BIT" "@ ldd RT'%A1,%0 - copy %1,%0 + copy %r1,%0 ldi %1,%0 ldil L'%1,%0 depdi,z %z1,%0 @@ -4246,13 +4246,13 @@ [(set (match_operand:DI 0 "move_dest_operand" "=r,r,r,r,r,r,Q,!*q,!r") (match_operand:DI 1 "move_src_operand" - "A,r,J,N,K,RQ,rM,!rM,!*q"))] + "A,rG,J,N,K,RQ,rM,!rM,!*q"))] "(register_operand (operands[0], DImode) || reg_or_0_operand (operands[1], DImode)) && TARGET_SOFT_FLOAT && TARGET_64BIT" "@ ldd RT'%A1,%0 - copy %1,%0 + copy %r1,%0 ldi %1,%0 ldil L'%1,%0 depdi,z %z1,%0