diff mbox series

[committed] hppa: Consistently use "rG" constraint for copy instruction in move patterns

Message ID a3743454-514a-4d7f-8a4d-4c59358b66a4@bell.net
State Committed
Headers
Series [committed] hppa: Consistently use "rG" constraint for copy instruction in move patterns |

Commit Message

John David Anglin Oct. 15, 2021, 3:13 p.m. UTC 
  Some move patterns on hppa use the "rG" constraint and some just use the "r" constraint
for the copy instruction.  This patch makes all the move patterns consistent.  It causes
a copy of register %r0 to always be used to zero a register.

There's no functional change since there are multiple ways to zero integer registers.

Tested on hppa2.0w-hp-hpux11.11 and hppa64-hp-hpux11.11.

Committed to active branches.

Dave
---
Consistently use "rG" constraint for copy instruction in move patterns

2021-10-15  John David Anglin  <danglin@gcc.gnu.org>

gcc/ChangeLog:

	* config/pa/pa.md: Consistently use "rG" constraint for copy
	instruction in move patterns.
diff mbox series

Patch

diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index 13a25381b6d..5cda3b79933 100644
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -2186,14 +2186,14 @@ 
    [(set (match_operand:SI 0 "move_dest_operand"
  			  "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T,?r,?*f")
  	(match_operand:SI 1 "move_src_operand"
-			  "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f,*f,r"))]
+			  "A,rG,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f,*f,r"))]
    "(register_operand (operands[0], SImode)
      || reg_or_0_operand (operands[1], SImode))
     && !TARGET_SOFT_FLOAT
     && !TARGET_64BIT"
    "@
     ldw RT'%A1,%0
-   copy %1,%0
+   copy %r1,%0
     ldi %1,%0
     ldil L'%1,%0
     {zdepi|depwi,z} %Z1,%0
@@ -2214,14 +2214,14 @@ 
    [(set (match_operand:SI 0 "move_dest_operand"
  			  "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T")
  	(match_operand:SI 1 "move_src_operand"
-			  "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f"))]
+			  "A,rG,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f"))]
    "(register_operand (operands[0], SImode)
      || reg_or_0_operand (operands[1], SImode))
     && !TARGET_SOFT_FLOAT
     && TARGET_64BIT"
    "@
     ldw RT'%A1,%0
-   copy %1,%0
+   copy %r1,%0
     ldi %1,%0
     ldil L'%1,%0
     {zdepi|depwi,z} %Z1,%0
@@ -2240,14 +2240,14 @@ 
    [(set (match_operand:SI 0 "move_dest_operand"
  			  "=r,r,r,r,r,r,Q,!*q,!r")
  	(match_operand:SI 1 "move_src_operand"
-			  "A,r,J,N,K,RQ,rM,!rM,!*q"))]
+			  "A,rG,J,N,K,RQ,rM,!rM,!*q"))]
    "(register_operand (operands[0], SImode)
      || reg_or_0_operand (operands[1], SImode))
     && TARGET_SOFT_FLOAT
     && TARGET_64BIT"
    "@
     ldw RT'%A1,%0
-   copy %1,%0
+   copy %r1,%0
     ldi %1,%0
     ldil L'%1,%0
     {zdepi|depwi,z} %Z1,%0
@@ -2381,13 +2381,13 @@ 
    [(set (match_operand:SI 0 "move_dest_operand"
  			  "=r,r,r,r,r,r,Q,!*q,!r")
  	(match_operand:SI 1 "move_src_operand"
-			  "A,r,J,N,K,RQ,rM,!rM,!*q"))]
+			  "A,rG,J,N,K,RQ,rM,!rM,!*q"))]
    "(register_operand (operands[0], SImode)
      || reg_or_0_operand (operands[1], SImode))
     && TARGET_SOFT_FLOAT"
    "@
     ldw RT'%A1,%0
-   copy %1,%0
+   copy %r1,%0
     ldi %1,%0
     ldil L'%1,%0
     {zdepi|depwi,z} %Z1,%0
@@ -2909,11 +2909,11 @@ 
    [(set (match_operand:HI 0 "move_dest_operand"
  	 		  "=r,r,r,r,r,Q,!*q,!r")
  	(match_operand:HI 1 "move_src_operand"
-			  "r,J,N,K,RQ,rM,!rM,!*q"))]
+			  "rG,J,N,K,RQ,rM,!rM,!*q"))]
    "(register_operand (operands[0], HImode)
      || reg_or_0_operand (operands[1], HImode))"
    "@
-   copy %1,%0
+   copy %r1,%0
     ldi %1,%0
     ldil L'%1,%0
     {zdepi|depwi,z} %Z1,%0
@@ -3069,11 +3069,11 @@ 
    [(set (match_operand:QI 0 "move_dest_operand"
  			  "=r,r,r,r,r,Q,!*q,!r")
  	(match_operand:QI 1 "move_src_operand"
-			  "r,J,N,K,RQ,rM,!rM,!*q"))]
+			  "rG,J,N,K,RQ,rM,!rM,!*q"))]
    "(register_operand (operands[0], QImode)
      || reg_or_0_operand (operands[1], QImode))"
    "@
-   copy %1,%0
+   copy %r1,%0
     ldi %1,%0
     ldil L'%1,%0
     {zdepi|depwi,z} %Z1,%0
@@ -4047,12 +4047,12 @@ 
    [(set (match_operand:DF 0 "move_dest_operand"
  			  "=!*r,*r,*r,*r,*r,Q,f,f,T")
  	(match_operand:DF 1 "move_src_operand"
-			  "!*r,J,N,K,RQ,*rG,fG,RT,f"))]
+			  "!*rG,J,N,K,RQ,*rG,fG,RT,f"))]
    "(register_operand (operands[0], DFmode)
      || reg_or_0_operand (operands[1], DFmode))
     && !TARGET_SOFT_FLOAT && TARGET_64BIT"
    "@
-   copy %1,%0
+   copy %r1,%0
     ldi %1,%0
     ldil L'%1,%0
     depdi,z %z1,%0
@@ -4069,12 +4069,12 @@ 
    [(set (match_operand:DF 0 "move_dest_operand"
  			  "=!*r,*r,*r,*r,*r,Q")
  	(match_operand:DF 1 "move_src_operand"
-			  "!*r,J,N,K,RQ,*rG"))]
+			  "!*rG,J,N,K,RQ,*rG"))]
    "(register_operand (operands[0], DFmode)
      || reg_or_0_operand (operands[1], DFmode))
     && TARGET_SOFT_FLOAT && TARGET_64BIT"
    "@
-   copy %1,%0
+   copy %r1,%0
     ldi %1,%0
     ldil L'%1,%0
     depdi,z %z1,%0
@@ -4221,13 +4221,13 @@ 
    [(set (match_operand:DI 0 "move_dest_operand"
  			  "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T")
  	(match_operand:DI 1 "move_src_operand"
-			  "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f"))]
+			  "A,rG,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f"))]
    "(register_operand (operands[0], DImode)
      || reg_or_0_operand (operands[1], DImode))
     && !TARGET_SOFT_FLOAT && TARGET_64BIT"
    "@
     ldd RT'%A1,%0
-   copy %1,%0
+   copy %r1,%0
     ldi %1,%0
     ldil L'%1,%0
     depdi,z %z1,%0
@@ -4246,13 +4246,13 @@ 
    [(set (match_operand:DI 0 "move_dest_operand"
  			  "=r,r,r,r,r,r,Q,!*q,!r")
  	(match_operand:DI 1 "move_src_operand"
-			  "A,r,J,N,K,RQ,rM,!rM,!*q"))]
+			  "A,rG,J,N,K,RQ,rM,!rM,!*q"))]
    "(register_operand (operands[0], DImode)
      || reg_or_0_operand (operands[1], DImode))
     && TARGET_SOFT_FLOAT && TARGET_64BIT"
    "@
     ldd RT'%A1,%0
-   copy %1,%0
+   copy %r1,%0
     ldi %1,%0
     ldil L'%1,%0
     depdi,z %z1,%0