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Fri, 25 Oct 2024 19:49:38 +0000 Received: from smtpav06.dal12v.mail.ibm.com (smtpav06.dal12v.mail.ibm.com [10.241.53.105]) by smtprelay01.wdc07v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 49PJnbjO39715460 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 25 Oct 2024 19:49:37 GMT Received: from smtpav06.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 2F09958059; Fri, 25 Oct 2024 19:49:37 +0000 (GMT) Received: from smtpav06.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C03D858055; Fri, 25 Oct 2024 19:49:36 +0000 (GMT) Received: from cowardly-lion.the-meissners.org (unknown [9.61.120.201]) by smtpav06.dal12v.mail.ibm.com (Postfix) with ESMTPS; Fri, 25 Oct 2024 19:49:36 +0000 (GMT) Date: Fri, 25 Oct 2024 15:49:35 -0400 From: Michael Meissner To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , "Kewen.Lin" , Peter Bergner Subject: [PATCH 8/11] Change TARGET_MODULO to TARGET_POWER9 Message-ID: Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , "Kewen.Lin" , Peter Bergner References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: d7DEfYoQg-qvy2puJt0J6DnU_kLGf0J3 X-Proofpoint-GUID: d7DEfYoQg-qvy2puJt0J6DnU_kLGf0J3 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1051,Hydra:6.0.680,FMLib:17.12.62.30 definitions=2024-10-15_01,2024-10-11_01,2024-09-30_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 suspectscore=0 phishscore=0 mlxlogscore=702 adultscore=0 spamscore=0 malwarescore=0 clxscore=1015 lowpriorityscore=0 bulkscore=0 mlxscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410250148 X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_NUMSUBJECT, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org As part of the architecture flags patches, this patch changes the use of TARGET_MODULO to TARGET_POWER9. The modulo instructions were added in power9 (ISA 3.0). Note, I did not change the uses of TARGET_MODULO where it was explicitly generating different code if the machine had a modulo instruction. I have built both big endian and little endian bootstrap compilers and there were no regressions. In addition, I constructed a test case that used every archiecture define (like _ARCH_PWR4, etc.) and I also looked at the .machine directive generated. I ran this test for all supported combinations of -mcpu, big/little endian, and 32/64 bit support. Every single instance generated exactly the same code with the patches installed compared to the compiler before installing the patches. Can I install this patch on the GCC 15 trunk? 2024-10-25 Michael Meissner * config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported): Use TARGET_POWER9 instead of TARGET_MODULO. * config/rs6000/rs6000.h (TARGET_CTZ): Likewise. (TARGET_EXTSWSLI): Likewise. (TARGET_MADDLD): Likewise. * config/rs6000/rs6000.md (enabled attribute): Likewise. --- gcc/config/rs6000/rs6000-builtin.cc | 4 ++-- gcc/config/rs6000/rs6000.h | 6 +++--- gcc/config/rs6000/rs6000.md | 2 +- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/gcc/config/rs6000/rs6000-builtin.cc b/gcc/config/rs6000/rs6000-builtin.cc index dae43b672ea..b6093b3cb64 100644 --- a/gcc/config/rs6000/rs6000-builtin.cc +++ b/gcc/config/rs6000/rs6000-builtin.cc @@ -169,9 +169,9 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins fncode) case ENB_P8V: return TARGET_P8_VECTOR; case ENB_P9: - return TARGET_MODULO; + return TARGET_POWER9; case ENB_P9_64: - return TARGET_MODULO && TARGET_POWERPC64; + return TARGET_POWER9 && TARGET_POWERPC64; case ENB_P9V: return TARGET_P9_VECTOR; case ENB_P10: diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 3a03c32f222..89ca1bad80f 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -461,9 +461,9 @@ extern int rs6000_vector_align[]; #define TARGET_FCTIWUZ TARGET_POWER7 /* Only powerpc64 and powerpc476 support fctid. */ #define TARGET_FCTID (TARGET_POWERPC64 || rs6000_cpu == PROCESSOR_PPC476) -#define TARGET_CTZ TARGET_MODULO -#define TARGET_EXTSWSLI (TARGET_MODULO && TARGET_POWERPC64) -#define TARGET_MADDLD TARGET_MODULO +#define TARGET_CTZ TARGET_POWER9 +#define TARGET_EXTSWSLI (TARGET_POWER9 && TARGET_POWERPC64) +#define TARGET_MADDLD TARGET_POWER9 /* TARGET_DIRECT_MOVE is redundant to TARGET_P8_VECTOR, so alias it to that. */ #define TARGET_DIRECT_MOVE TARGET_P8_VECTOR diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index bff898a4eff..fc0d454e9a4 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -403,7 +403,7 @@ (define_attr "enabled" "" (const_int 1) (and (eq_attr "isa" "p9") - (match_test "TARGET_MODULO")) + (match_test "TARGET_POWER9")) (const_int 1) (and (eq_attr "isa" "p9v")