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Fri, 25 Oct 2024 19:48:35 +0000 Received: from smtpav06.wdc07v.mail.ibm.com (smtpav06.wdc07v.mail.ibm.com [10.39.53.233]) by smtprelay02.wdc07v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 49PJmY5O29426334 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 25 Oct 2024 19:48:34 GMT Received: from smtpav06.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 3DC9358054; Fri, 25 Oct 2024 19:48:34 +0000 (GMT) Received: from smtpav06.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 7FC185803F; Fri, 25 Oct 2024 19:48:33 +0000 (GMT) Received: from cowardly-lion.the-meissners.org (unknown [9.61.120.201]) by smtpav06.wdc07v.mail.ibm.com (Postfix) with ESMTPS; Fri, 25 Oct 2024 19:48:33 +0000 (GMT) Date: Fri, 25 Oct 2024 15:48:31 -0400 From: Michael Meissner To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , "Kewen.Lin" , Peter Bergner Subject: [PATCH 7/11] Change TARGET_POPCNTD to TARGET_POWER7 Message-ID: Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , "Kewen.Lin" , Peter Bergner References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: E5I5ehgLqt2QqQfUnUxQb7ZAWe-OTIGs X-Proofpoint-GUID: E5I5ehgLqt2QqQfUnUxQb7ZAWe-OTIGs X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1051,Hydra:6.0.680,FMLib:17.12.62.30 definitions=2024-10-15_01,2024-10-11_01,2024-09-30_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 mlxscore=0 bulkscore=0 suspectscore=0 spamscore=0 phishscore=0 adultscore=0 priorityscore=1501 clxscore=1015 lowpriorityscore=0 malwarescore=0 mlxlogscore=962 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410250148 X-Spam-Status: No, score=-10.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_NUMSUBJECT, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org As part of the architecture flags patches, this patch changes the use of TARGET_POPCNTD to TARGET_POWER7. The POPCNTD instruction was added in power7 (ISA 2.06). I have built both big endian and little endian bootstrap compilers and there were no regressions. In addition, I constructed a test case that used every archiecture define (like _ARCH_PWR4, etc.) and I also looked at the .machine directive generated. I ran this test for all supported combinations of -mcpu, big/little endian, and 32/64 bit support. Every single instance generated exactly the same code with the patches installed compared to the compiler before installing the patches. Can I install this patch on the GCC 15 trunk? 2024-10-25 Michael Meissner * config/rs6000/dfp.md (floatdidd2): Change TARGET_POPCNTD to TARGET_POWER7. * config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported): Likewise. * config/rs6000/rs6000-string.cc (expand_block_compare_gpr): Likewise. * config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached): Likewise. (rs6000_rtx_costs): Likewise. (rs6000_emit_popcount): Likewise. * config/rs6000/rs6000.h (TARGET_LDBRX): Likewise. (TARGET_LFIWZX): Likewise. (TARGET_FCFIDS): Likewise. (TARGET_FCFIDU): Likewise. (TARGET_FCFIDUS): Likewise. (TARGET_FCTIDUZ): Likewise. (TARGET_FCTIWUZ): Likewise. (CTZ_DEFINED_VALUE_AT_ZERO): Likewise. * config/rs6000/rs6000.md (enabled attribute): Likewise. (ctz2): Likewise. (popcntd2): Likewise. (lrintsi2): Likewise. (lrintsi): Likewise. (lrintsi_di): Likewise. (cmpmemsi): Likewise. (bpermd_"): Likewise. (addg6s): Likewise. (cdtbcd): Likewise. (cbcdtd): Likewise. (div_): Likewise. --- gcc/config/rs6000/dfp.md | 2 +- gcc/config/rs6000/rs6000-builtin.cc | 4 ++-- gcc/config/rs6000/rs6000-string.cc | 4 ++-- gcc/config/rs6000/rs6000.cc | 6 +++--- gcc/config/rs6000/rs6000.h | 16 ++++++++-------- gcc/config/rs6000/rs6000.md | 24 ++++++++++++------------ 6 files changed, 28 insertions(+), 28 deletions(-) diff --git a/gcc/config/rs6000/dfp.md b/gcc/config/rs6000/dfp.md index fa9d7dd45dd..b8189390d41 100644 --- a/gcc/config/rs6000/dfp.md +++ b/gcc/config/rs6000/dfp.md @@ -214,7 +214,7 @@ (define_insn "*cmp_internal1" (define_insn "floatdidd2" [(set (match_operand:DD 0 "gpc_reg_operand" "=d") (float:DD (match_operand:DI 1 "gpc_reg_operand" "d")))] - "TARGET_DFP && TARGET_POPCNTD" + "TARGET_DFP && TARGET_POWER7" "dcffix %0,%1" [(set_attr "type" "dfp")]) diff --git a/gcc/config/rs6000/rs6000-builtin.cc b/gcc/config/rs6000/rs6000-builtin.cc index 76421bd1de0..dae43b672ea 100644 --- a/gcc/config/rs6000/rs6000-builtin.cc +++ b/gcc/config/rs6000/rs6000-builtin.cc @@ -161,9 +161,9 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins fncode) case ENB_P6_64: return TARGET_POWER6 && TARGET_POWERPC64; case ENB_P7: - return TARGET_POPCNTD; + return TARGET_POWER7; case ENB_P7_64: - return TARGET_POPCNTD && TARGET_POWERPC64; + return TARGET_POWER7 && TARGET_POWERPC64; case ENB_P8: return TARGET_POWER8; case ENB_P8V: diff --git a/gcc/config/rs6000/rs6000-string.cc b/gcc/config/rs6000/rs6000-string.cc index 55b4133b1a3..3674c4bd984 100644 --- a/gcc/config/rs6000/rs6000-string.cc +++ b/gcc/config/rs6000/rs6000-string.cc @@ -1948,8 +1948,8 @@ expand_block_compare_gpr(unsigned HOST_WIDE_INT bytes, unsigned int base_align, bool expand_block_compare (rtx operands[]) { - /* TARGET_POPCNTD is already guarded at expand cmpmemsi. */ - gcc_assert (TARGET_POPCNTD); + /* TARGET_POWER7 is already guarded at expand cmpmemsi. */ + gcc_assert (TARGET_POWER7); /* For P8, this case is complicated to handle because the subtract with carry instructions do not generate the 64-bit carry and so diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index dd51d75c495..7d20e757c7c 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -1999,7 +1999,7 @@ rs6000_hard_regno_mode_ok_uncached (int regno, machine_mode mode) if(GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD) return 1; - if (TARGET_POPCNTD && mode == SImode) + if (TARGET_POWER7 && mode == SImode) return 1; if (TARGET_P9_VECTOR && (mode == QImode || mode == HImode)) @@ -22473,7 +22473,7 @@ rs6000_rtx_costs (rtx x, machine_mode mode, int outer_code, return false; case POPCOUNT: - *total = COSTS_N_INSNS (TARGET_POPCNTD ? 1 : 6); + *total = COSTS_N_INSNS (TARGET_POWER7 ? 1 : 6); return false; case PARITY: @@ -23260,7 +23260,7 @@ rs6000_emit_popcount (rtx dst, rtx src) rtx tmp1, tmp2; /* Use the PPC ISA 2.06 popcnt{w,d} instruction if we can. */ - if (TARGET_POPCNTD) + if (TARGET_POWER7) { if (mode == SImode) emit_insn (gen_popcntdsi2 (dst, src)); diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index d22693eb2bf..3a03c32f222 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -442,7 +442,7 @@ extern int rs6000_vector_align[]; #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size > 64) #define TARGET_IEEEQUAD rs6000_ieeequad #define TARGET_ALTIVEC_ABI rs6000_altivec_abi -#define TARGET_LDBRX (TARGET_POPCNTD || rs6000_cpu == PROCESSOR_CELL) +#define TARGET_LDBRX (TARGET_POWER7 || rs6000_cpu == PROCESSOR_CELL) /* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only. Enable 32-bit fcfid's on any of the switches for newer ISA machines. */ @@ -453,12 +453,12 @@ extern int rs6000_vector_align[]; #define TARGET_FCTIDZ TARGET_FCFID #define TARGET_STFIWX TARGET_PPC_GFXOPT #define TARGET_LFIWAX TARGET_POWER6 -#define TARGET_LFIWZX TARGET_POPCNTD -#define TARGET_FCFIDS TARGET_POPCNTD -#define TARGET_FCFIDU TARGET_POPCNTD -#define TARGET_FCFIDUS TARGET_POPCNTD -#define TARGET_FCTIDUZ TARGET_POPCNTD -#define TARGET_FCTIWUZ TARGET_POPCNTD +#define TARGET_LFIWZX TARGET_POWER7 +#define TARGET_FCFIDS TARGET_POWER7 +#define TARGET_FCFIDU TARGET_POWER7 +#define TARGET_FCFIDUS TARGET_POWER7 +#define TARGET_FCTIDUZ TARGET_POWER7 +#define TARGET_FCTIWUZ TARGET_POWER7 /* Only powerpc64 and powerpc476 support fctid. */ #define TARGET_FCTID (TARGET_POWERPC64 || rs6000_cpu == PROCESSOR_PPC476) #define TARGET_CTZ TARGET_MODULO @@ -1754,7 +1754,7 @@ typedef struct rs6000_args zero. The hardware instructions added in Power9 and the sequences using popcount return 32 or 64. */ #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ - (TARGET_CTZ || TARGET_POPCNTD \ + (TARGET_CTZ || TARGET_POWER7 \ ? ((VALUE) = GET_MODE_BITSIZE (MODE), 2) \ : ((VALUE) = -1, 2)) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 0c303087e94..bff898a4eff 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -387,7 +387,7 @@ (define_attr "enabled" "" (const_int 1) (and (eq_attr "isa" "p7") - (match_test "TARGET_POPCNTD")) + (match_test "TARGET_POWER7")) (const_int 1) (and (eq_attr "isa" "p7v") @@ -2466,7 +2466,7 @@ (define_expand "ctz2" rtx tmp2 = gen_reg_rtx (mode); rtx tmp3 = gen_reg_rtx (mode); - if (TARGET_POPCNTD) + if (TARGET_POWER7) { emit_insn (gen_add3 (tmp1, operands[1], constm1_rtx)); emit_insn (gen_one_cmpl2 (tmp2, operands[1])); @@ -2527,7 +2527,7 @@ (define_insn "popcntb2" (define_insn "popcntd2" [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))] - "TARGET_POPCNTD" + "TARGET_POWER7" "popcnt %0,%1" [(set_attr "type" "popcnt")]) @@ -6784,7 +6784,7 @@ (define_expand "lrintsi2" /* For those old archs in which SImode can't be hold in float registers, call lrintsi_di to put the result in DImode then convert it via stack. */ - if (!TARGET_POPCNTD) + if (!TARGET_POWER7) { rtx tmp = gen_reg_rtx (DImode); emit_insn (gen_lrintsi_di (tmp, operands[1])); @@ -6799,7 +6799,7 @@ (define_insn "*lrintsi" [(set (match_operand:SI 0 "gpc_reg_operand" "=d") (unspec:SI [(match_operand:SFDF 1 "gpc_reg_operand" "")] UNSPEC_FCTIW))] - "TARGET_HARD_FLOAT && TARGET_POPCNTD" + "TARGET_HARD_FLOAT && TARGET_POWER7" "fctiw %0,%1" [(set_attr "type" "fp")]) @@ -6807,7 +6807,7 @@ (define_insn "lrintsi_di" [(set (match_operand:DI 0 "gpc_reg_operand" "=d") (unspec:DI [(match_operand:SFDF 1 "gpc_reg_operand" "")] UNSPEC_FCTIW))] - "TARGET_HARD_FLOAT && !TARGET_POPCNTD" + "TARGET_HARD_FLOAT && !TARGET_POWER7" "fctiw %0,%1" [(set_attr "type" "fp")]) @@ -10168,7 +10168,7 @@ (define_expand "cmpmemsi" (match_operand:BLK 2))) (use (match_operand:SI 3)) (use (match_operand:SI 4))])] - "TARGET_POPCNTD" + "TARGET_POWER7" { if (optimize_insn_for_size_p ()) FAIL; @@ -14435,7 +14435,7 @@ (define_insn "bpermd_" [(set (match_operand:P 0 "gpc_reg_operand" "=r") (unspec:P [(match_operand:P 1 "gpc_reg_operand" "r") (match_operand:P 2 "gpc_reg_operand" "r")] UNSPEC_BPERM))] - "TARGET_POPCNTD" + "TARGET_POWER7" "bpermd %0,%1,%2" [(set_attr "type" "popcnt")]) @@ -14813,7 +14813,7 @@ (define_insn "addg6s" (unspec:SI [(match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "register_operand" "r")] UNSPEC_ADDG6S))] - "TARGET_POPCNTD" + "TARGET_POWER7" "addg6s %0,%1,%2" [(set_attr "type" "integer")]) @@ -14821,7 +14821,7 @@ (define_insn "cdtbcd" [(set (match_operand:SI 0 "register_operand" "=r") (unspec:SI [(match_operand:SI 1 "register_operand" "r")] UNSPEC_CDTBCD))] - "TARGET_POPCNTD" + "TARGET_POWER7" "cdtbcd %0,%1" [(set_attr "type" "integer")]) @@ -14829,7 +14829,7 @@ (define_insn "cbcdtd" [(set (match_operand:SI 0 "register_operand" "=r") (unspec:SI [(match_operand:SI 1 "register_operand" "r")] UNSPEC_CBCDTD))] - "TARGET_POPCNTD" + "TARGET_POWER7" "cbcdtd %0,%1" [(set_attr "type" "integer")]) @@ -14844,7 +14844,7 @@ (define_insn "div_" (unspec:GPR [(match_operand:GPR 1 "register_operand" "r") (match_operand:GPR 2 "register_operand" "r")] UNSPEC_DIV_EXTEND))] - "TARGET_POPCNTD" + "TARGET_POWER7" "div %0,%1,%2" [(set_attr "type" "div") (set_attr "size" "")])