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Fri, 25 Oct 2024 19:47:13 +0000 Received: from smtpav04.dal12v.mail.ibm.com (smtpav04.dal12v.mail.ibm.com [10.241.53.103]) by smtprelay07.wdc07v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 49PJlBXN5571216 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 25 Oct 2024 19:47:11 GMT Received: from smtpav04.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 922995805A; Fri, 25 Oct 2024 19:47:11 +0000 (GMT) Received: from smtpav04.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 2FC4658052; Fri, 25 Oct 2024 19:47:11 +0000 (GMT) Received: from cowardly-lion.the-meissners.org (unknown [9.61.120.201]) by smtpav04.dal12v.mail.ibm.com (Postfix) with ESMTPS; Fri, 25 Oct 2024 19:47:11 +0000 (GMT) Date: Fri, 25 Oct 2024 15:47:09 -0400 From: Michael Meissner To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , "Kewen.Lin" , Peter Bergner Subject: [PATCH 6/11] Change TARGET_CMPB to TARGET_POWER6 Message-ID: Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , "Kewen.Lin" , Peter Bergner References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-TM-AS-GCONF: 00 X-Proofpoint-GUID: lRaJ52o7jylohB6Ola3o-gTS2rQt8-qv X-Proofpoint-ORIG-GUID: lRaJ52o7jylohB6Ola3o-gTS2rQt8-qv X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1051,Hydra:6.0.680,FMLib:17.12.62.30 definitions=2024-10-15_01,2024-10-11_01,2024-09-30_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 lowpriorityscore=0 phishscore=0 spamscore=0 mlxscore=0 mlxlogscore=723 priorityscore=1501 suspectscore=0 clxscore=1015 impostorscore=0 bulkscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410250148 X-Spam-Status: No, score=-10.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_NUMSUBJECT, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org As part of the architecture flags patches, this patch changes the use of TARGET_CMPB to TARGET_POWER6. The CMPB instruction was added in power6 (ISA 2.05). I have built both big endian and little endian bootstrap compilers and there were no regressions. In addition, I constructed a test case that used every archiecture define (like _ARCH_PWR4, etc.) and I also looked at the .machine directive generated. I ran this test for all supported combinations of -mcpu, big/little endian, and 32/64 bit support. Every single instance generated exactly the same code with the patches installed compared to the compiler before installing the patches. Can I install this patch on the GCC 15 trunk? 2024-10-25 Michael Meissner * config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported): Use TARGET_POWER6 instead of TARGET_CMPB. * config/rs6000/rs6000.h (TARGET_FCFID): Merge tests for popcntb, cmpb, and popcntd into a single test for TARGET_POWER5. (TARGET_LFIWAX): Use TARGET_POWER6 instead of TARGET_CMPB. * config/rs6000/rs6000.md (enabled attribute): Likewise. (parity2_cmp): Likewise. (cmpb): Likewise. (copysign3): Likewise. (copysign3_fcpsgn): Likewise. (cmpstrnsi): Likewise. (cmpstrsi): Likewise. --- gcc/config/rs6000/rs6000-builtin.cc | 4 ++-- gcc/config/rs6000/rs6000.h | 6 ++---- gcc/config/rs6000/rs6000.md | 16 ++++++++-------- 3 files changed, 12 insertions(+), 14 deletions(-) diff --git a/gcc/config/rs6000/rs6000-builtin.cc b/gcc/config/rs6000/rs6000-builtin.cc index 98a0545030c..76421bd1de0 100644 --- a/gcc/config/rs6000/rs6000-builtin.cc +++ b/gcc/config/rs6000/rs6000-builtin.cc @@ -157,9 +157,9 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins fncode) case ENB_P5: return TARGET_POWER5; case ENB_P6: - return TARGET_CMPB; + return TARGET_POWER6; case ENB_P6_64: - return TARGET_CMPB && TARGET_POWERPC64; + return TARGET_POWER6 && TARGET_POWERPC64; case ENB_P7: return TARGET_POPCNTD; case ENB_P7_64: diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 4500724d895..d22693eb2bf 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -448,13 +448,11 @@ extern int rs6000_vector_align[]; Enable 32-bit fcfid's on any of the switches for newer ISA machines. */ #define TARGET_FCFID (TARGET_POWERPC64 \ || TARGET_PPC_GPOPT /* 970/power4 */ \ - || TARGET_POPCNTB /* ISA 2.02 */ \ - || TARGET_CMPB /* ISA 2.05 */ \ - || TARGET_POPCNTD) /* ISA 2.06 */ + || TARGET_POWER5) /* ISA 2.02 and above */ \ #define TARGET_FCTIDZ TARGET_FCFID #define TARGET_STFIWX TARGET_PPC_GFXOPT -#define TARGET_LFIWAX TARGET_CMPB +#define TARGET_LFIWAX TARGET_POWER6 #define TARGET_LFIWZX TARGET_POPCNTD #define TARGET_FCFIDS TARGET_POPCNTD #define TARGET_FCFIDU TARGET_POPCNTD diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 7f9fe609a03..0c303087e94 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -383,7 +383,7 @@ (define_attr "enabled" "" (const_int 1) (and (eq_attr "isa" "p6") - (match_test "TARGET_CMPB")) + (match_test "TARGET_POWER6")) (const_int 1) (and (eq_attr "isa" "p7") @@ -2544,7 +2544,7 @@ (define_expand "parity2" (define_insn "parity2_cmpb" [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")] UNSPEC_PARITY))] - "TARGET_CMPB" + "TARGET_POWER6" "prty %0,%1" [(set_attr "type" "popcnt")]) @@ -2597,7 +2597,7 @@ (define_insn "cmpb3" [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r") (match_operand:GPR 2 "gpc_reg_operand" "r")] UNSPEC_CMPB))] - "TARGET_CMPB" + "TARGET_POWER6" "cmpb %0,%1,%2" [(set_attr "type" "cmp")]) @@ -5401,7 +5401,7 @@ (define_expand "copysign3" && ((TARGET_PPC_GFXOPT && !HONOR_NANS (mode) && !HONOR_SIGNED_ZEROS (mode)) - || TARGET_CMPB + || TARGET_POWER6 || VECTOR_UNIT_VSX_P (mode))" { /* Middle-end canonicalizes -fabs (x) to copysign (x, -1), @@ -5422,7 +5422,7 @@ (define_expand "copysign3" if (!gpc_reg_operand (operands[2], mode)) operands[2] = copy_to_mode_reg (mode, operands[2]); - if (TARGET_CMPB || VECTOR_UNIT_VSX_P (mode)) + if (TARGET_POWER6 || VECTOR_UNIT_VSX_P (mode)) { emit_insn (gen_copysign3_fcpsgn (operands[0], operands[1], operands[2])); @@ -5438,7 +5438,7 @@ (define_insn "copysign3_fcpsgn" [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa") (copysign:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "d,wa") (match_operand:SFDF 2 "gpc_reg_operand" "d,wa")))] - "TARGET_HARD_FLOAT && (TARGET_CMPB || VECTOR_UNIT_VSX_P (mode))" + "TARGET_HARD_FLOAT && (TARGET_POWER6 || VECTOR_UNIT_VSX_P (mode))" "@ fcpsgn %0,%2,%1 xscpsgndp %x0,%x2,%x1" @@ -10122,7 +10122,7 @@ (define_expand "cmpstrnsi" (match_operand:BLK 2))) (use (match_operand:SI 3)) (use (match_operand:SI 4))])] - "TARGET_CMPB && (BYTES_BIG_ENDIAN || TARGET_LDBRX)" + "TARGET_POWER6 && (BYTES_BIG_ENDIAN || TARGET_LDBRX)" { if (optimize_insn_for_size_p ()) FAIL; @@ -10144,7 +10144,7 @@ (define_expand "cmpstrsi" (compare:SI (match_operand:BLK 1) (match_operand:BLK 2))) (use (match_operand:SI 3))])] - "TARGET_CMPB && (BYTES_BIG_ENDIAN || TARGET_LDBRX)" + "TARGET_POWER6 && (BYTES_BIG_ENDIAN || TARGET_LDBRX)" { if (optimize_insn_for_size_p ()) FAIL;