[REPOST,2/3] Add tuning support for power11

Message ID Zo7Gcy2apiHGz2Ye@cowardly-lion.the-meissners.org
State New
Headers
Series Add support for -mcpu=power11 |

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Commit Message

Michael Meissner July 10, 2024, 5:35 p.m. UTC
  [This is a repost of the June 4th patch]

This patch makes -mtune=power11 use the same tuning decisions as -mtune=power10.

This patch makes -mtune=power11 use the same tuning decisions as
-mtune=power10.  It needs the previous patch to be applied.

I have bootstrapped these patches on both little endian and big endian systems.
Can I check these changes into the GCC 15 trunk.  After a waiting period, can I
check these patches into the GCC 14 branch?

2024-07-10  Michael Meissner  <meissner@linux.ibm.com>

gcc/

	* config/rs6000/power10.md (all reservations): Add power11 as an
	alternative to power10.
---
 gcc/config/rs6000/power10.md | 144 +++++++++++++++++------------------
 1 file changed, 72 insertions(+), 72 deletions(-)
  

Comments

Segher Boessenkool July 18, 2024, 1:14 p.m. UTC | #1
Hi!

On Wed, Jul 10, 2024 at 01:35:47PM -0400, Michael Meissner wrote:
> 	* config/rs6000/power10.md (all reservations): Add power11 as an
> 	alternative to power10.

That is not a great description of what is actually going on.  Just
"Add power11." would be better :-)  Or "Add power11 behaving identically
to power10." if you want to say that.

> --- a/gcc/config/rs6000/power10.md
> +++ b/gcc/config/rs6000/power10.md
> @@ -1,4 +1,4 @@
> -;; Scheduling description for the IBM POWER10 processor.
> +;; Scheduling description for the IBM POWER10 and POWER11 processors.

The official names are Power10 and Power11 (only the P a capital).

Okay for trunk with that fixed.  Also okay for backport to 14.  (After
the usual burn-in period of course).  Thanks!


Segher
  

Patch

diff --git a/gcc/config/rs6000/power10.md b/gcc/config/rs6000/power10.md
index fcc2199ab29..90312643858 100644
--- a/gcc/config/rs6000/power10.md
+++ b/gcc/config/rs6000/power10.md
@@ -1,4 +1,4 @@ 
-;; Scheduling description for the IBM POWER10 processor.
+;; Scheduling description for the IBM POWER10 and POWER11 processors.
 ;; Copyright (C) 2020-2024 Free Software Foundation, Inc.
 ;;
 ;; Contributed by Pat Haugen (pthaugen@us.ibm.com).
@@ -97,12 +97,12 @@  (define_insn_reservation "power10-load" 4
        (eq_attr "update" "no")
        (eq_attr "size" "!128")
        (eq_attr "prefixed" "no")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,LU_power10")
 
 (define_insn_reservation "power10-fused-load" 4
   (and (eq_attr "type" "fused_load_cmpi,fused_addis_load,fused_load_load")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_even_power10,LU_power10")
 
 (define_insn_reservation "power10-prefixed-load" 4
@@ -110,13 +110,13 @@  (define_insn_reservation "power10-prefixed-load" 4
        (eq_attr "update" "no")
        (eq_attr "size" "!128")
        (eq_attr "prefixed" "yes")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_even_power10,LU_power10")
 
 (define_insn_reservation "power10-load-update" 4
   (and (eq_attr "type" "load")
        (eq_attr "update" "yes")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_even_power10,LU_power10+SXU_power10")
 
 (define_insn_reservation "power10-fpload-double" 4
@@ -124,7 +124,7 @@  (define_insn_reservation "power10-fpload-double" 4
        (eq_attr "update" "no")
        (eq_attr "size" "64")
        (eq_attr "prefixed" "no")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,LU_power10")
 
 (define_insn_reservation "power10-prefixed-fpload-double" 4
@@ -132,14 +132,14 @@  (define_insn_reservation "power10-prefixed-fpload-double" 4
        (eq_attr "update" "no")
        (eq_attr "size" "64")
        (eq_attr "prefixed" "yes")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_even_power10,LU_power10")
 
 (define_insn_reservation "power10-fpload-update-double" 4
   (and (eq_attr "type" "fpload")
        (eq_attr "update" "yes")
        (eq_attr "size" "64")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_even_power10,LU_power10+SXU_power10")
 
 ; SFmode loads are cracked and have additional 3 cycles over DFmode
@@ -148,27 +148,27 @@  (define_insn_reservation "power10-fpload-single" 7
   (and (eq_attr "type" "fpload")
        (eq_attr "update" "no")
        (eq_attr "size" "32")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_even_power10,LU_power10")
 
 (define_insn_reservation "power10-fpload-update-single" 7
   (and (eq_attr "type" "fpload")
        (eq_attr "update" "yes")
        (eq_attr "size" "32")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_even_power10,LU_power10+SXU_power10")
 
 (define_insn_reservation "power10-vecload" 4
   (and (eq_attr "type" "vecload")
        (eq_attr "size" "!256")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,LU_power10")
 
 ; lxvp
 (define_insn_reservation "power10-vecload-pair" 4
   (and (eq_attr "type" "vecload")
        (eq_attr "size" "256")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_even_power10,LU_power10+SXU_power10")
 
 ; Store Unit
@@ -178,12 +178,12 @@  (define_insn_reservation "power10-store" 0
        (eq_attr "prefixed" "no")
        (eq_attr "size" "!128")
        (eq_attr "size" "!256")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,STU_power10")
 
 (define_insn_reservation "power10-fused-store" 0
   (and (eq_attr "type" "fused_store_store")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_even_power10,STU_power10")
 
 (define_insn_reservation "power10-prefixed-store" 0
@@ -191,52 +191,52 @@  (define_insn_reservation "power10-prefixed-store" 0
        (eq_attr "prefixed" "yes")
        (eq_attr "size" "!128")
        (eq_attr "size" "!256")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_even_power10,STU_power10")
 
 ; Update forms have 2 cycle latency for updated addr reg
 (define_insn_reservation "power10-store-update" 2
   (and (eq_attr "type" "store,fpstore")
        (eq_attr "update" "yes")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,STU_power10")
 
 ; stxvp
 (define_insn_reservation "power10-vecstore-pair" 0
   (and (eq_attr "type" "vecstore")
        (eq_attr "size" "256")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_even_power10,stu0_power10+stu1_power10")
 
 (define_insn_reservation "power10-larx" 4
   (and (eq_attr "type" "load_l")
        (eq_attr "size" "!128")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,LU_power10")
 
 ; All load quad forms
 (define_insn_reservation "power10-lq" 4
   (and (eq_attr "type" "load,load_l")
        (eq_attr "size" "128")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_even_power10,LU_power10+SXU_power10")
 
 (define_insn_reservation "power10-stcx" 0
   (and (eq_attr "type" "store_c")
        (eq_attr "size" "!128")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,STU_power10")
 
 ; All store quad forms
 (define_insn_reservation "power10-stq" 0
   (and (eq_attr "type" "store,store_c")
        (eq_attr "size" "128")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_even_power10,stu0_power10+stu1_power10")
 
 (define_insn_reservation "power10-sync" 1
   (and (eq_attr "type" "sync,isync")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_even_power10,STU_power10")
 
 
@@ -248,7 +248,7 @@  (define_insn_reservation "power10-sync" 1
 (define_insn_reservation "power10-alu" 2
   (and (eq_attr "type" "add,exts,integer,logical,isel")
        (eq_attr "prefixed" "no")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 ; 4 cycle CR latency
 (define_bypass 4 "power10-alu"
@@ -256,28 +256,28 @@  (define_bypass 4 "power10-alu"
 
 (define_insn_reservation "power10-fused_alu" 2
   (and (eq_attr "type" "fused_arith_logical,fused_cmp_isel,fused_carry")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_even_power10,EXU_power10")
 
 ; paddi
 (define_insn_reservation "power10-paddi" 2
   (and (eq_attr "type" "add")
        (eq_attr "prefixed" "yes")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_even_power10,EXU_power10")
 
 ; Rotate/shift (non-record form)
 (define_insn_reservation "power10-rot" 2
   (and (eq_attr "type" "insert,shift")
        (eq_attr "dot" "no")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 
 ; Record form rotate/shift
 (define_insn_reservation "power10-rot-compare" 3
   (and (eq_attr "type" "insert,shift")
        (eq_attr "dot" "yes")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 ; 5 cycle CR latency
 (define_bypass 5 "power10-rot-compare"
@@ -285,7 +285,7 @@  (define_bypass 5 "power10-rot-compare"
 
 (define_insn_reservation "power10-alu2" 3
   (and (eq_attr "type" "cntlz,popcnt,trap")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 ; 5 cycle CR latency
 (define_bypass 5 "power10-alu2"
@@ -293,24 +293,24 @@  (define_bypass 5 "power10-alu2"
 
 (define_insn_reservation "power10-cmp" 2
   (and (eq_attr "type" "cmp")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 
 ; Treat 'two' and 'three' types as 2 or 3 way cracked
 (define_insn_reservation "power10-two" 4
   (and (eq_attr "type" "two")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_even_power10,EXU_power10")
 
 (define_insn_reservation "power10-three" 6
   (and (eq_attr "type" "three")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_all_power10,EXU_power10")
 
 (define_insn_reservation "power10-mul" 5
   (and (eq_attr "type" "mul")
        (eq_attr "dot" "no")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 ; 4 cycle MUL->MUL latency
 (define_bypass 4 "power10-mul"
@@ -319,7 +319,7 @@  (define_bypass 4 "power10-mul"
 (define_insn_reservation "power10-mul-compare" 5
   (and (eq_attr "type" "mul")
        (eq_attr "dot" "yes")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_even_power10,EXU_power10")
 ; 4 cycle MUL->MUL latency
 (define_bypass 4 "power10-mul-compare"
@@ -331,13 +331,13 @@  (define_bypass 7 "power10-mul-compare"
 (define_insn_reservation "power10-div" 12
   (and (eq_attr "type" "div")
        (eq_attr "dot" "no")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-div-compare" 12
   (and (eq_attr "type" "div")
        (eq_attr "dot" "yes")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_even_power10,EXU_power10")
 ; 14 cycle CR latency
 (define_bypass 14 "power10-div-compare"
@@ -345,34 +345,34 @@  (define_bypass 14 "power10-div-compare"
 
 (define_insn_reservation "power10-crlogical" 2
   (and (eq_attr "type" "cr_logical")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-mfcrf" 2
   (and (eq_attr "type" "mfcrf")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-mfcr" 3
   (and (eq_attr "type" "mfcr")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_even_power10,EXU_power10")
 
 ; Should differentiate between 1 cr field and > 1 since target of > 1 cr
 ; is cracked
 (define_insn_reservation "power10-mtcr" 3
   (and (eq_attr "type" "mtcr")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-mtjmpr" 3
   (and (eq_attr "type" "mtjmpr")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-mfjmpr" 2
   (and (eq_attr "type" "mfjmpr")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 
 
@@ -380,126 +380,126 @@  (define_insn_reservation "power10-mfjmpr" 2
 
 (define_insn_reservation "power10-fpsimple" 3
   (and (eq_attr "type" "fpsimple")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-fp" 5
   (and (eq_attr "type" "fp,dmul")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-fpcompare" 3
   (and (eq_attr "type" "fpcompare")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-sdiv" 22
   (and (eq_attr "type" "sdiv")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-ddiv" 27
   (and (eq_attr "type" "ddiv")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-sqrt" 26
   (and (eq_attr "type" "ssqrt")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-dsqrt" 36
   (and (eq_attr "type" "dsqrt")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-vec-2cyc" 2
   (and (eq_attr "type" "vecmove,veclogical,vecexts,veccmpfx")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-fused-vec" 2
   (and (eq_attr "type" "fused_vector")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_even_power10,EXU_power10")
 
 (define_insn_reservation "power10-veccmp" 3
   (and (eq_attr "type" "veccmp")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-vecsimple" 2
   (and (eq_attr "type" "vecsimple")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-vecnormal" 5
   (and (eq_attr "type" "vecfloat,vecdouble")
        (eq_attr "size" "!128")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-qp" 12
   (and (eq_attr "type" "vecfloat,vecdouble")
        (eq_attr "size" "128")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-vecperm" 3
   (and (eq_attr "type" "vecperm")
        (eq_attr "prefixed" "no")
        (eq_attr "dot" "no")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-vecperm-compare" 3
   (and (eq_attr "type" "vecperm")
        (eq_attr "dot" "yes")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_even_power10,EXU_power10")
 
 (define_insn_reservation "power10-prefixed-vecperm" 3
   (and (eq_attr "type" "vecperm")
        (eq_attr "prefixed" "yes")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_even_power10,EXU_power10")
 
 (define_insn_reservation "power10-veccomplex" 6
   (and (eq_attr "type" "veccomplex")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-vecfdiv" 24
   (and (eq_attr "type" "vecfdiv")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-vecdiv" 27
   (and (eq_attr "type" "vecdiv")
        (eq_attr "size" "!128")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-qpdiv" 56
   (and (eq_attr "type" "vecdiv")
        (eq_attr "size" "128")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-qpmul" 24
   (and (eq_attr "type" "qmul")
        (eq_attr "size" "128")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-mtvsr" 2
   (and (eq_attr "type" "mtvsr")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-mfvsr" 2
   (and (eq_attr "type" "mfvsr")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 
 
@@ -507,26 +507,26 @@  (define_insn_reservation "power10-mfvsr" 2
 ; Branch is 2 cycles, grouped with STU for issue
 (define_insn_reservation "power10-branch" 2
   (and (eq_attr "type" "jmpreg,branch")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,STU_power10")
 
 (define_insn_reservation "power10-fused-branch" 3
   (and (eq_attr "type" "fused_mtbc")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_even_power10,STU_power10")
 
 
 ; Crypto
 (define_insn_reservation "power10-crypto" 4
   (and (eq_attr "type" "crypto")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 
 
 ; HTM
 (define_insn_reservation "power10-htm" 2
   (and (eq_attr "type" "htmsimple,htm")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 
 
@@ -535,26 +535,26 @@  (define_insn_reservation "power10-htm" 2
 (define_insn_reservation "power10-dfp" 12
   (and (eq_attr "type" "dfp")
        (eq_attr "size" "!128")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-dfpq" 12
   (and (eq_attr "type" "dfp")
        (eq_attr "size" "128")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_even_power10,EXU_power10")
 
 ; MMA
 (define_insn_reservation "power10-mma" 9
   (and (eq_attr "type" "mma")
        (eq_attr "prefixed" "no")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_super_power10")
 
 (define_insn_reservation "power10-prefixed-mma" 9
   (and (eq_attr "type" "mma")
        (eq_attr "prefixed" "yes")
-       (eq_attr "cpu" "power10"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_even_power10,EXU_super_power10")
 ; 4 cycle MMA->MMA latency
 (define_bypass 4 "power10-mma,power10-prefixed-mma"