[REPOST,1/3] Add support for -mcpu=power11
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Commit Message
[This is a repost of the June 4th patch]
This patch adds the power11 option to the -mcpu= and -mtune= switches.
This patch treats the power11 like a power10 in terms of costs and reassociation
width.
This patch issues a ".machine power11" to the assembly file if you use
-mcpu=power11.
This patch defines _ARCH_PWR11 if the user uses -mcpu=power11.
This patch allows GCC to be configured with the --with-cpu=power11 and
--with-tune=power11 options.
This patch passes -mpwr11 to the assembler if the user uses -mcpu=power11.
This patch adds support for using "power11" in the __builtin_cpu_is built-in
function.
2024-07-02 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config.gcc (rs6000*-*-*, powerpc*-*-*): Add support for power11.
* config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for -mcpu=power11.
* config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/driver-rs6000.cc (asm_names): Likewise.
* config/rs6000/ppc-auxv.h (PPC_PLATFORM_POWER11): New define.
* config/rs6000/rs6000-builtin.cc (cpu_is_info): Add power11.
* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define
_ARCH_PWR11 if -mcpu=power11.
* config/rs6000/rs6000-cpus.def (ISA_POWER11_MASKS_SERVER): New define.
(POWERPC_MASKS): Add power11 isa bit.
(power11 cpu): Add power11 definition.
* config/rs6000/rs6000-opts.h (PROCESSOR_POWER11): Add power11 processor.
* config/rs6000/rs6000-string.cc (expand_compare_loop): Likewise.
* config/rs6000/rs6000-tables.opt: Regenerate.
* config/rs6000/rs6000.cc (rs6000_option_override_internal): Add power11
support.
(rs6000_machine_from_flags): Likewise.
(rs6000_reassociation_width): Likewise.
(rs6000_adjust_cost): Likewise.
(rs6000_issue_rate): Likewise.
(rs6000_sched_reorder): Likewise.
(rs6000_sched_reorder2): Likewise.
(rs6000_register_move_cost): Likewise.
(rs6000_opt_masks): Likewise.
* config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/rs6000.md (cpu attribute): Add power11.
* config/rs6000/rs6000.opt (-mpower11): Add internal power11 ISA flag.
* doc/invoke.texi (RS/6000 and PowerPC Options): Document -mcpu=power11.
---
gcc/config.gcc | 6 ++++--
gcc/config/rs6000/aix71.h | 1 +
gcc/config/rs6000/aix72.h | 1 +
gcc/config/rs6000/aix73.h | 1 +
gcc/config/rs6000/driver-rs6000.cc | 2 ++
gcc/config/rs6000/ppc-auxv.h | 3 +--
gcc/config/rs6000/rs6000-builtin.cc | 1 +
gcc/config/rs6000/rs6000-c.cc | 2 ++
gcc/config/rs6000/rs6000-cpus.def | 5 +++++
gcc/config/rs6000/rs6000-opts.h | 3 ++-
gcc/config/rs6000/rs6000-string.cc | 1 +
gcc/config/rs6000/rs6000-tables.opt | 3 +++
gcc/config/rs6000/rs6000.cc | 32 +++++++++++++++++++++--------
gcc/config/rs6000/rs6000.h | 1 +
gcc/config/rs6000/rs6000.md | 2 +-
gcc/config/rs6000/rs6000.opt | 3 +++
gcc/doc/invoke.texi | 5 +++--
17 files changed, 56 insertions(+), 16 deletions(-)
Comments
Hi!
[ I reviewed this together with Ke Wen. All blame should go to me, all
praise to him. ]
On Wed, Jul 10, 2024 at 01:34:26PM -0400, Michael Meissner wrote:
> [This is a repost of the June 4th patch]
It is not a repost. It is v2. It has important changes.
> * config.gcc (rs6000*-*-*, powerpc*-*-*): Add support for power11.
Please do not add new rs6000-* stuff. There haven't been systems like
that for twenty years or so now. It is mostly harmless to add this
stuff, but it just makes more work to delete later. And more
importantly, this was not tested; this *cannot* be tested.
> * config/rs6000/rs6000-cpus.def (ISA_POWER11_MASKS_SERVER): New define.
> (POWERPC_MASKS): Add power11 isa bit.
There is no Power11 ISA bit. There cannnot be a Power11 ISA bit. There
is no new ISA for Power11.
"Add power11 bit"? It is a hack to easily distinguish between power10
and power11, nothing more. It abuses existing mechanisms a bit. Not
the nicest thing to do, but it works :-)
But please do not call it what it is not. And mark it up as a hack in
some nice place.
> * config/rs6000/rs6000.opt (-mpower11): Add internal power11 ISA flag.
s//ISA //
It is not nice to have a user-selectable option for this at all :-(
> --- a/gcc/config.gcc
> +++ b/gcc/config.gcc
> @@ -533,7 +533,9 @@ powerpc*-*-*)
> extra_headers="${extra_headers} ppu_intrinsics.h spu2vmx.h vec_types.h si2vmx.h"
> extra_headers="${extra_headers} amo.h"
> case x$with_cpu in
> - xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower10|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500)
> + xpowerpc64 | xdefault64 | x6[23]0 | x970 | xG5 | xpower[3456789] \
> + | xpower1[01] | xpower6x | xrs64a | xcell | xa2 | xe500mc64 \
> + | xe5500 | xe6500)
> cpu_is_64bit=yes
> ;;
> esac
Please do not change form and function at the same time. It is much
easier to see what is going on, to verify the change is correct, if you
do it as two patches (either the cleanup first, which is nicer, or as a
later step, which is often easier).
> --- a/gcc/config/rs6000/ppc-auxv.h
> +++ b/gcc/config/rs6000/ppc-auxv.h
> @@ -47,9 +47,8 @@
> #define PPC_PLATFORM_PPC476 12
> #define PPC_PLATFORM_POWER8 13
> #define PPC_PLATFORM_POWER9 14
> -
> -/* This is not yet official. */
> #define PPC_PLATFORM_POWER10 15
> +#define PPC_PLATFORM_POWER11 16
Please add a comment where the official thing is?
It is in glibc dl-procinfo.h, and there *cannot* be more than 16
platforms currently, so how can this work? Or do we get data
directly from the kernel, or what?
But you tested it, so you do obviously get PPC_PLATFORM_POWER11 from
somewhere. I cannot see from where though?
> --- a/gcc/config/rs6000/rs6000-opts.h
> +++ b/gcc/config/rs6000/rs6000-opts.h
> @@ -67,7 +67,8 @@ enum processor_type
> PROCESSOR_MPCCORE,
> PROCESSOR_CELL,
> PROCESSOR_PPCA2,
> - PROCESSOR_TITAN
> + PROCESSOR_TITAN,
> + PROCESSOR_POWER11
Please insert this after the p10 entry. There is a (very vague)
ordering here, we do not put the newest at the end.
> -/* Instruction costs on POWER10 processors. */
> +/* Instruction costs on POWER10/POWER11 processors. */
The official names are Power10 and Power11. POWER9 is still in SHOUTING
CAPS, but later CPUs have the more relaxed spelling as official names
(just like the Power ISA has had for longer already).
> - /* Do Power10 dependent reordering. */
> - if (rs6000_tune == PROCESSOR_POWER10 && last_scheduled_insn)
> + /* Do Power10/power11 dependent reordering. */
Power11.
> + /* Do Power10/power11 dependent reordering. */
Again.
> --- a/gcc/config/rs6000/rs6000.md
> +++ b/gcc/config/rs6000/rs6000.md
> @@ -351,7 +351,7 @@ (define_attr "cpu"
> ppc403,ppc405,ppc440,ppc476,
> ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500,
> power4,power5,power6,power7,power8,power9,power10,
> - rs64a,mpccore,cell,ppca2,titan"
> + rs64a,mpccore,cell,ppca2,titan,power11"
Add this after power10.
> --- a/gcc/config/rs6000/rs6000.opt
> +++ b/gcc/config/rs6000/rs6000.opt
> @@ -585,6 +585,9 @@ Target Undocumented Var(rs6000_speculate_indirect_jumps) Init(1) Save
> mpower10
> Target Undocumented Mask(POWER10) Var(rs6000_isa_flags) WarnRemoved
>
> +mpower11
> +Target Undocumented Mask(POWER11) Var(rs6000_isa_flags) Warn(Do not use %<-mpower11>)
So why have this option at all? It is a hack because you want to look
at this bitfield instead of the "which cpu/tune do we have selected"
field in some places? That is only acceptable if you do not hide that
fact!
Why is it not "WarnRemoved" like mpower10 is? That wasn't factually
true there either. Emulating this manually with some custom Warn is
farther from ideal.
It would be much better if we did not need to use an ugly hack like
this. Future improvement :-)
> --- a/gcc/doc/invoke.texi
> +++ b/gcc/doc/invoke.texi
> @@ -31488,8 +31488,9 @@ Supported values for @var{cpu_type} are @samp{401}, @samp{403},
> @samp{e6500}, @samp{ec603e}, @samp{G3}, @samp{G4}, @samp{G5},
> @samp{titan}, @samp{power3}, @samp{power4}, @samp{power5}, @samp{power5+},
> @samp{power6}, @samp{power6x}, @samp{power7}, @samp{power8},
> -@samp{power9}, @samp{power10}, @samp{powerpc}, @samp{powerpc64},
> -@samp{powerpc64le}, @samp{rs64}, and @samp{native}.
> +@samp{power9}, @samp{power10}, @samp{power11},
> +@samp{powerpc}, @samp{powerpc64}, @samp{powerpc64le},
> +@samp{rs64}, and @samp{native}.
Hint: you do not need to layout TeXinfo source code. TeX itself takes
care of that much better than you can. It is fine to keep some short
lines, this will be rewrapped in output anyway.
Okay for trunk with those changes. Also fine for backport to 14.
Thank you!
Segher
On Thu, Jul 18, 2024 at 08:08:44AM -0500, Segher Boessenkool wrote:
> Hi!
>
> [ I reviewed this together with Ke Wen. All blame should go to me, all
> praise to him. ]
>
> On Wed, Jul 10, 2024 at 01:34:26PM -0400, Michael Meissner wrote:
> > [This is a repost of the June 4th patch]
>
> It is not a repost. It is v2. It has important changes.
The first 2 patches for the compiler proper are exactly the same as the June
4th post. Yes, the June 4th post had changes from the previous post.
The only change was to the testsuite.
> > * config.gcc (rs6000*-*-*, powerpc*-*-*): Add support for power11.
>
> Please do not add new rs6000-* stuff. There haven't been systems like
> that for twenty years or so now. It is mostly harmless to add this
> stuff, but it just makes more work to delete later. And more
> importantly, this was not tested; this *cannot* be tested.
The code I added was just extra code in the powerpc section. I did not change
the case statement. That code had the rs6000* line, so I was just quoting it
in the ChangeLog.
>
> > * config/rs6000/rs6000-cpus.def (ISA_POWER11_MASKS_SERVER): New define.
> > (POWERPC_MASKS): Add power11 isa bit.
>
> There is no Power11 ISA bit. There cannnot be a Power11 ISA bit. There
> is no new ISA for Power11.
>
> "Add power11 bit"? It is a hack to easily distinguish between power10
> and power11, nothing more. It abuses existing mechanisms a bit. Not
> the nicest thing to do, but it works :-)
>
> But please do not call it what it is not. And mark it up as a hack in
> some nice place.
The issue is right now the mechanism to distinguish between the cpus is the
bits in rs6000_isa_flags. Sure other mechanisms can be done, and perhaps we
should create them, but if you want the correct defines and .machines to be
done for things like #pragma GCC tar and the target attribute, the simplest way
is to create a new bit in rs6000_isa_flags, and just mark the option as giving
an error if the user explicity uses it.
> > * config/rs6000/rs6000.opt (-mpower11): Add internal power11 ISA flag.
>
> s//ISA //
>
> It is not nice to have a user-selectable option for this at all :-(
>
> > --- a/gcc/config.gcc
> > +++ b/gcc/config.gcc
> > @@ -533,7 +533,9 @@ powerpc*-*-*)
> > extra_headers="${extra_headers} ppu_intrinsics.h spu2vmx.h vec_types.h si2vmx.h"
> > extra_headers="${extra_headers} amo.h"
> > case x$with_cpu in
> > - xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower10|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500)
> > + xpowerpc64 | xdefault64 | x6[23]0 | x970 | xG5 | xpower[3456789] \
> > + | xpower1[01] | xpower6x | xrs64a | xcell | xa2 | xe500mc64 \
> > + | xe5500 | xe6500)
> > cpu_is_64bit=yes
> > ;;
> > esac
>
> Please do not change form and function at the same time. It is much
> easier to see what is going on, to verify the change is correct, if you
> do it as two patches (either the cleanup first, which is nicer, or as a
> later step, which is often easier).
I can just make the line even longer if you prefer.
> > --- a/gcc/config/rs6000/ppc-auxv.h
> > +++ b/gcc/config/rs6000/ppc-auxv.h
> > @@ -47,9 +47,8 @@
> > #define PPC_PLATFORM_PPC476 12
> > #define PPC_PLATFORM_POWER8 13
> > #define PPC_PLATFORM_POWER9 14
> > -
> > -/* This is not yet official. */
> > #define PPC_PLATFORM_POWER10 15
> > +#define PPC_PLATFORM_POWER11 16
>
> Please add a comment where the official thing is?
>
> It is in glibc dl-procinfo.h, and there *cannot* be more than 16
> platforms currently, so how can this work? Or do we get data
> directly from the kernel, or what?
>
> But you tested it, so you do obviously get PPC_PLATFORM_POWER11 from
> somewhere. I cannot see from where though?
In other discussions, I was told that 16 with be the platform number for the
kernel in the future.
> > --- a/gcc/config/rs6000/rs6000-opts.h
> > +++ b/gcc/config/rs6000/rs6000-opts.h
> > @@ -67,7 +67,8 @@ enum processor_type
> > PROCESSOR_MPCCORE,
> > PROCESSOR_CELL,
> > PROCESSOR_PPCA2,
> > - PROCESSOR_TITAN
> > + PROCESSOR_TITAN,
> > + PROCESSOR_POWER11
>
> Please insert this after the p10 entry. There is a (very vague)
> ordering here, we do not put the newest at the end.
Ok.
> > -/* Instruction costs on POWER10 processors. */
> > +/* Instruction costs on POWER10/POWER11 processors. */
>
> The official names are Power10 and Power11. POWER9 is still in SHOUTING
> CAPS, but later CPUs have the more relaxed spelling as official names
> (just like the Power ISA has had for longer already).
Ok, but I was just using the current code's format.
> > - /* Do Power10 dependent reordering. */
> > - if (rs6000_tune == PROCESSOR_POWER10 && last_scheduled_insn)
> > + /* Do Power10/power11 dependent reordering. */
>
> Power11.
Ok.
> > + /* Do Power10/power11 dependent reordering. */
>
> Again.
>
> > --- a/gcc/config/rs6000/rs6000.md
> > +++ b/gcc/config/rs6000/rs6000.md
> > @@ -351,7 +351,7 @@ (define_attr "cpu"
> > ppc403,ppc405,ppc440,ppc476,
> > ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500,
> > power4,power5,power6,power7,power8,power9,power10,
> > - rs64a,mpccore,cell,ppca2,titan"
> > + rs64a,mpccore,cell,ppca2,titan,power11"
>
> Add this after power10.
Ok.
> > --- a/gcc/config/rs6000/rs6000.opt
> > +++ b/gcc/config/rs6000/rs6000.opt
> > @@ -585,6 +585,9 @@ Target Undocumented Var(rs6000_speculate_indirect_jumps) Init(1) Save
> > mpower10
> > Target Undocumented Mask(POWER10) Var(rs6000_isa_flags) WarnRemoved
> >
> > +mpower11
> > +Target Undocumented Mask(POWER11) Var(rs6000_isa_flags) Warn(Do not use %<-mpower11>)
>
> So why have this option at all? It is a hack because you want to look
> at this bitfield instead of the "which cpu/tune do we have selected"
> field in some places? That is only acceptable if you do not hide that
> fact!
>
> Why is it not "WarnRemoved" like mpower10 is? That wasn't factually
> true there either. Emulating this manually with some custom Warn is
> farther from ideal.
>
> It would be much better if we did not need to use an ugly hack like
> this. Future improvement :-)
Ok.
> > --- a/gcc/doc/invoke.texi
> > +++ b/gcc/doc/invoke.texi
> > @@ -31488,8 +31488,9 @@ Supported values for @var{cpu_type} are @samp{401}, @samp{403},
> > @samp{e6500}, @samp{ec603e}, @samp{G3}, @samp{G4}, @samp{G5},
> > @samp{titan}, @samp{power3}, @samp{power4}, @samp{power5}, @samp{power5+},
> > @samp{power6}, @samp{power6x}, @samp{power7}, @samp{power8},
> > -@samp{power9}, @samp{power10}, @samp{powerpc}, @samp{powerpc64},
> > -@samp{powerpc64le}, @samp{rs64}, and @samp{native}.
> > +@samp{power9}, @samp{power10}, @samp{power11},
> > +@samp{powerpc}, @samp{powerpc64}, @samp{powerpc64le},
> > +@samp{rs64}, and @samp{native}.
>
> Hint: you do not need to layout TeXinfo source code. TeX itself takes
> care of that much better than you can. It is fine to keep some short
> lines, this will be rewrapped in output anyway.
Ok.
> Okay for trunk with those changes. Also fine for backport to 14.
> Thank you!
>
>
> Segher
On 7/19/24 12:34 PM, Michael Meissner wrote:
> On Thu, Jul 18, 2024 at 08:08:44AM -0500, Segher Boessenkool wrote:
>>> --- a/gcc/config/rs6000/ppc-auxv.h
>>> +++ b/gcc/config/rs6000/ppc-auxv.h
>>> @@ -47,9 +47,8 @@
>>> #define PPC_PLATFORM_PPC476 12
>>> #define PPC_PLATFORM_POWER8 13
>>> #define PPC_PLATFORM_POWER9 14
>>> -
>>> -/* This is not yet official. */
>>> #define PPC_PLATFORM_POWER10 15
>>> +#define PPC_PLATFORM_POWER11 16
>>
>> Please add a comment where the official thing is?
>>
>> It is in glibc dl-procinfo.h, and there *cannot* be more than 16
>> platforms currently, so how can this work? Or do we get data
>> directly from the kernel, or what?
>>
>> But you tested it, so you do obviously get PPC_PLATFORM_POWER11 from
>> somewhere. I cannot see from where though?
>
> In other discussions, I was told that 16 with be the platform number for the
> kernel in the future.
The AT_PLATFORM from the kernel is a string, not an integer.
To make __builtin_cpu_is ("power11") work efficiently, GLIBC stores
an integer representing each cpu AT_PLATFORM string in the TCB.
It is therefore GLIBC which "owns" the integer versions of the
platform values and yes, 16 is the correct value for Power11 and
that value exists in upstream GLIBC.
Peter
@@ -533,7 +533,9 @@ powerpc*-*-*)
extra_headers="${extra_headers} ppu_intrinsics.h spu2vmx.h vec_types.h si2vmx.h"
extra_headers="${extra_headers} amo.h"
case x$with_cpu in
- xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower10|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500)
+ xpowerpc64 | xdefault64 | x6[23]0 | x970 | xG5 | xpower[3456789] \
+ | xpower1[01] | xpower6x | xrs64a | xcell | xa2 | xe500mc64 \
+ | xe5500 | xe6500)
cpu_is_64bit=yes
;;
esac
@@ -5641,7 +5643,7 @@ case "${target}" in
eval "with_$which=405"
;;
"" | common | native \
- | power[3456789] | power10 | power5+ | power6x \
+ | power[3456789] | power1[01] | power5+ | power6x \
| powerpc | powerpc64 | powerpc64le \
| rs64 \
| 401 | 403 | 405 | 405fp | 440 | 440fp | 464 | 464fp \
@@ -79,6 +79,7 @@ do { \
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
+ mcpu=power11: -mpwr11; \
mcpu=power10: -mpwr10; \
mcpu=power9: -mpwr9; \
mcpu=power8: -mpwr8; \
@@ -79,6 +79,7 @@ do { \
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
+ mcpu=power11: -mpwr11; \
mcpu=power10: -mpwr10; \
mcpu=power9: -mpwr9; \
mcpu=power8: -mpwr8; \
@@ -79,6 +79,7 @@ do { \
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
+ mcpu=power11: -mpwr11; \
mcpu=power10: -mpwr10; \
mcpu=power9: -mpwr9; \
mcpu=power8: -mpwr8; \
@@ -451,6 +451,7 @@ static const struct asm_name asm_names[] = {
{ "power8", "-mpwr8" },
{ "power9", "-mpwr9" },
{ "power10", "-mpwr10" },
+ { "power11", "-mpwr11" },
{ "powerpc", "-mppc" },
{ "rs64", "-mppc" },
{ "603", "-m603" },
@@ -479,6 +480,7 @@ static const struct asm_name asm_names[] = {
{ "power8", "-mpower8" },
{ "power9", "-mpower9" },
{ "power10", "-mpower10" },
+ { "power11", "-mpower11" },
{ "a2", "-ma2" },
{ "powerpc", "-mppc" },
{ "powerpc64", "-mppc64" },
@@ -47,9 +47,8 @@
#define PPC_PLATFORM_PPC476 12
#define PPC_PLATFORM_POWER8 13
#define PPC_PLATFORM_POWER9 14
-
-/* This is not yet official. */
#define PPC_PLATFORM_POWER10 15
+#define PPC_PLATFORM_POWER11 16
/* AT_HWCAP bits. These must match the values defined in the Linux kernel. */
#define PPC_FEATURE_32 0x80000000
@@ -2496,6 +2496,7 @@ static const struct
const char *cpu;
unsigned int cpuid;
} cpu_is_info[] = {
+ { "power11", PPC_PLATFORM_POWER11 },
{ "power10", PPC_PLATFORM_POWER10 },
{ "power9", PPC_PLATFORM_POWER9 },
{ "power8", PPC_PLATFORM_POWER8 },
@@ -435,6 +435,8 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR9");
if ((flags & OPTION_MASK_POWER10) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR10");
+ if ((flags & OPTION_MASK_POWER11) != 0)
+ rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR11");
if ((flags & OPTION_MASK_SOFT_FLOAT) != 0)
rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT");
if ((flags & OPTION_MASK_RECIP_PRECISION) != 0)
@@ -86,6 +86,9 @@
| OPTION_MASK_POWER10 \
| OTHER_POWER10_MASKS)
+#define ISA_POWER11_MASKS_SERVER (ISA_3_1_MASKS_SERVER \
+ | OPTION_MASK_POWER11)
+
/* Flags that need to be turned off if -mno-vsx. */
#define OTHER_VSX_VECTOR_MASKS (OPTION_MASK_EFFICIENT_UNALIGNED_VSX \
| OPTION_MASK_FLOAT128_KEYWORD \
@@ -123,6 +126,7 @@
| OPTION_MASK_FLOAT128_KEYWORD \
| OPTION_MASK_FPRND \
| OPTION_MASK_POWER10 \
+ | OPTION_MASK_POWER11 \
| OPTION_MASK_P10_FUSION \
| OPTION_MASK_HTM \
| OPTION_MASK_ISEL \
@@ -256,3 +260,4 @@ RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, OPTION_MASK_PPC_GFXOPT
RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64
| ISA_2_7_MASKS_SERVER | OPTION_MASK_HTM)
RS6000_CPU ("rs64", PROCESSOR_RS64A, OPTION_MASK_PPC_GFXOPT | MASK_POWERPC64)
+RS6000_CPU ("power11", PROCESSOR_POWER11, MASK_POWERPC64 | ISA_POWER11_MASKS_SERVER)
@@ -67,7 +67,8 @@ enum processor_type
PROCESSOR_MPCCORE,
PROCESSOR_CELL,
PROCESSOR_PPCA2,
- PROCESSOR_TITAN
+ PROCESSOR_TITAN,
+ PROCESSOR_POWER11
};
@@ -964,6 +964,7 @@ expand_compare_loop (rtx operands[])
break;
case PROCESSOR_POWER9:
case PROCESSOR_POWER10:
+ case PROCESSOR_POWER11:
if (bytes_is_const)
max_bytes = 191;
else
@@ -197,3 +197,6 @@ Enum(rs6000_cpu_opt_value) String(powerpc64le) Value(55)
EnumValue
Enum(rs6000_cpu_opt_value) String(rs64) Value(56)
+EnumValue
+Enum(rs6000_cpu_opt_value) String(power11) Value(57)
+
@@ -1067,7 +1067,7 @@ struct processor_costs power9_cost = {
COSTS_N_INSNS (3), /* SF->DF convert */
};
-/* Instruction costs on POWER10 processors. */
+/* Instruction costs on POWER10/POWER11 processors. */
static const
struct processor_costs power10_cost = {
COSTS_N_INSNS (2), /* mulsi */
@@ -4385,7 +4385,8 @@ rs6000_option_override_internal (bool global_init_p)
generating power10 instructions. */
if (!(rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION))
{
- if (rs6000_tune == PROCESSOR_POWER10)
+ if (rs6000_tune == PROCESSOR_POWER10
+ || rs6000_tune == PROCESSOR_POWER11)
rs6000_isa_flags |= OPTION_MASK_P10_FUSION;
else
rs6000_isa_flags &= ~OPTION_MASK_P10_FUSION;
@@ -4414,6 +4415,7 @@ rs6000_option_override_internal (bool global_init_p)
&& rs6000_tune != PROCESSOR_POWER8
&& rs6000_tune != PROCESSOR_POWER9
&& rs6000_tune != PROCESSOR_POWER10
+ && rs6000_tune != PROCESSOR_POWER11
&& rs6000_tune != PROCESSOR_PPCA2
&& rs6000_tune != PROCESSOR_CELL
&& rs6000_tune != PROCESSOR_PPC476);
@@ -4428,6 +4430,7 @@ rs6000_option_override_internal (bool global_init_p)
|| rs6000_tune == PROCESSOR_POWER8
|| rs6000_tune == PROCESSOR_POWER9
|| rs6000_tune == PROCESSOR_POWER10
+ || rs6000_tune == PROCESSOR_POWER11
|| rs6000_tune == PROCESSOR_PPCE500MC
|| rs6000_tune == PROCESSOR_PPCE500MC64
|| rs6000_tune == PROCESSOR_PPCE5500
@@ -4727,6 +4730,7 @@ rs6000_option_override_internal (bool global_init_p)
break;
case PROCESSOR_POWER10:
+ case PROCESSOR_POWER11:
rs6000_cost = &power10_cost;
break;
@@ -5886,6 +5890,8 @@ rs6000_machine_from_flags (void)
/* Disable the flags that should never influence the .machine selection. */
flags &= ~(OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT | OPTION_MASK_ISEL);
+ if ((flags & (ISA_POWER11_MASKS_SERVER & ~ISA_3_1_MASKS_SERVER)) != 0)
+ return "power11";
if ((flags & (ISA_3_1_MASKS_SERVER & ~ISA_3_0_MASKS_SERVER)) != 0)
return "power10";
if ((flags & (ISA_3_0_MASKS_SERVER & ~ISA_2_7_MASKS_SERVER)) != 0)
@@ -10132,6 +10138,7 @@ rs6000_reassociation_width (unsigned int opc ATTRIBUTE_UNUSED,
case PROCESSOR_POWER8:
case PROCESSOR_POWER9:
case PROCESSOR_POWER10:
+ case PROCESSOR_POWER11:
if (DECIMAL_FLOAT_MODE_P (mode))
return 1;
if (VECTOR_MODE_P (mode))
@@ -18213,7 +18220,8 @@ rs6000_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn, int cost,
/* Separate a load from a narrower, dependent store. */
if ((rs6000_sched_groups || rs6000_tune == PROCESSOR_POWER9
- || rs6000_tune == PROCESSOR_POWER10)
+ || rs6000_tune == PROCESSOR_POWER10
+ || rs6000_tune == PROCESSOR_POWER11)
&& GET_CODE (PATTERN (insn)) == SET
&& GET_CODE (PATTERN (dep_insn)) == SET
&& MEM_P (XEXP (PATTERN (insn), 1))
@@ -18252,6 +18260,7 @@ rs6000_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn, int cost,
|| rs6000_tune == PROCESSOR_POWER8
|| rs6000_tune == PROCESSOR_POWER9
|| rs6000_tune == PROCESSOR_POWER10
+ || rs6000_tune == PROCESSOR_POWER11
|| rs6000_tune == PROCESSOR_CELL)
&& recog_memoized (dep_insn)
&& (INSN_CODE (dep_insn) >= 0))
@@ -18826,6 +18835,7 @@ rs6000_issue_rate (void)
case PROCESSOR_POWER9:
return 6;
case PROCESSOR_POWER10:
+ case PROCESSOR_POWER11:
return 8;
default:
return 1;
@@ -19541,8 +19551,10 @@ rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED, int sched_verbose,
if (rs6000_tune == PROCESSOR_POWER6)
load_store_pendulum = 0;
- /* Do Power10 dependent reordering. */
- if (rs6000_tune == PROCESSOR_POWER10 && last_scheduled_insn)
+ /* Do Power10/power11 dependent reordering. */
+ if (last_scheduled_insn
+ && (rs6000_tune == PROCESSOR_POWER10
+ || rs6000_tune == PROCESSOR_POWER11))
power10_sched_reorder (ready, n_ready - 1);
return rs6000_issue_rate ();
@@ -19566,8 +19578,10 @@ rs6000_sched_reorder2 (FILE *dump, int sched_verbose, rtx_insn **ready,
&& recog_memoized (last_scheduled_insn) >= 0)
return power9_sched_reorder2 (ready, *pn_ready - 1);
- /* Do Power10 dependent reordering. */
- if (rs6000_tune == PROCESSOR_POWER10 && last_scheduled_insn)
+ /* Do Power10/power11 dependent reordering. */
+ if (last_scheduled_insn
+ && (rs6000_tune == PROCESSOR_POWER10
+ || rs6000_tune == PROCESSOR_POWER11))
return power10_sched_reorder (ready, *pn_ready - 1);
return cached_can_issue_more;
@@ -22784,7 +22798,8 @@ rs6000_register_move_cost (machine_mode mode,
allocation a move within the same class might turn
out to be a nop. */
if (rs6000_tune == PROCESSOR_POWER9
- || rs6000_tune == PROCESSOR_POWER10)
+ || rs6000_tune == PROCESSOR_POWER10
+ || rs6000_tune == PROCESSOR_POWER11)
ret = 3 * hard_regno_nregs (FIRST_GPR_REGNO, mode);
else
ret = 4 * hard_regno_nregs (FIRST_GPR_REGNO, mode);
@@ -24456,6 +24471,7 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
{ "float128-hardware", OPTION_MASK_FLOAT128_HW, false, true },
{ "fprnd", OPTION_MASK_FPRND, false, true },
{ "power10", OPTION_MASK_POWER10, false, true },
+ { "power11", OPTION_MASK_POWER11, false, false },
{ "hard-dfp", OPTION_MASK_DFP, false, true },
{ "htm", OPTION_MASK_HTM, false, true },
{ "isel", OPTION_MASK_ISEL, false, true },
@@ -106,6 +106,7 @@
you make changes here, make them also there. */
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
+ mcpu=power11: -mpower11; \
mcpu=power10: -mpower10; \
mcpu=power9: -mpower9; \
mcpu=power8|mcpu=powerpc64le: -mpower8; \
@@ -351,7 +351,7 @@ (define_attr "cpu"
ppc403,ppc405,ppc440,ppc476,
ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500,
power4,power5,power6,power7,power8,power9,power10,
- rs64a,mpccore,cell,ppca2,titan"
+ rs64a,mpccore,cell,ppca2,titan,power11"
(const (symbol_ref "(enum attr_cpu) rs6000_tune")))
;; The ISA we implement.
@@ -585,6 +585,9 @@ Target Undocumented Var(rs6000_speculate_indirect_jumps) Init(1) Save
mpower10
Target Undocumented Mask(POWER10) Var(rs6000_isa_flags) WarnRemoved
+mpower11
+Target Undocumented Mask(POWER11) Var(rs6000_isa_flags) Warn(Do not use %<-mpower11>)
+
mprefixed
Target Mask(PREFIXED) Var(rs6000_isa_flags)
Generate (do not generate) prefixed memory instructions.
@@ -31488,8 +31488,9 @@ Supported values for @var{cpu_type} are @samp{401}, @samp{403},
@samp{e6500}, @samp{ec603e}, @samp{G3}, @samp{G4}, @samp{G5},
@samp{titan}, @samp{power3}, @samp{power4}, @samp{power5}, @samp{power5+},
@samp{power6}, @samp{power6x}, @samp{power7}, @samp{power8},
-@samp{power9}, @samp{power10}, @samp{powerpc}, @samp{powerpc64},
-@samp{powerpc64le}, @samp{rs64}, and @samp{native}.
+@samp{power9}, @samp{power10}, @samp{power11},
+@samp{powerpc}, @samp{powerpc64}, @samp{powerpc64le},
+@samp{rs64}, and @samp{native}.
@option{-mcpu=powerpc}, @option{-mcpu=powerpc64}, and
@option{-mcpu=powerpc64le} specify pure 32-bit PowerPC (either