diff mbox series

LoongArch: Fix up [su]dot_prod*

Message ID Z9FfIeWH8lXoq4S5@tucnak
State New
Headers
Series LoongArch: Fix up [su]dot_prod* |

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Commit Message

Jakub Jelinek March 12, 2025, 10:17 a.m. UTC 
  On Fri, Feb 14, 2025 at 08:21:39PM +0800, Xi Ruoyao wrote:
> +(define_expand "<su>dot_prod<wvec_half><mode>"
> +  [(match_operand:<WVEC_HALF> 0 "register_operand" "=f,f")
> +   (match_operand:IVEC	      1 "register_operand" " f,f")
> +   (match_operand:IVEC	      2 "register_operand" " f,f")
> +   (match_operand:<WVEC_HALF> 3 "reg_or_0_operand" " 0,YG")
> +   (any_extend (const_int 0))]
> +  ""
> +{
> +  auto [op0, op1, op2, op3] = operands;

GCC is written in C++14 these days and will be for a few years, we've
just switched from C++11 to C++14.
The above construct is C++17, so not appropriate in GCC sources
(at least not conditionalized on C++ version).
Furthermore, if it was added to help formatting, I think it still
didn't help much, the emit_insn (
on one line and argument on another is just ugly.  The problem
aren't the not so long operands[0] etc. arguments, but the too long
names of the gen_* functions.

> +
> +  if (op3 == CONST0_RTX (<WVEC_HALF>mode))
> +    emit_insn (
> +      gen_<simd_isa>_<x>vmulwev_<simdfmt_w>_<simdfmt><u> (op0, op1, op2));
> +  else
> +    emit_insn (
> +      gen_<simd_isa>_<x>vmaddwev_<simdfmt_w>_<simdfmt><u> (op0, op3, op1,
> +							   op2));
> +
> +  emit_insn (
> +    gen_<simd_isa>_<x>vmaddwod_<simdfmt_w>_<simdfmt><u> (op0, op0, op1, op2));
> +  DONE;
> +})

So, I'd suggest following instead.

Tested by building a cross until cc1/cc1plus is built (I don't have binutils
built for the target around).

Ok for trunk?

2025-03-12  Jakub Jelinek  <jakub@redhat.com>

	PR target/119238
	* config/loongarch/simd.md (<su>dot_prod<wvec_half><mode>): Don't use
	structured bindings.  Instead, use function pointers to improve
	formatting.



	Jakub
diff mbox series

Patch

--- gcc/config/loongarch/simd.md.jj	2025-03-05 06:39:50.198297885 +0100
+++ gcc/config/loongarch/simd.md	2025-03-12 10:42:05.769933119 +0100
@@ -809,18 +809,21 @@  (define_expand "<su>dot_prod<wvec_half><
    (any_extend (const_int 0))]
   ""
 {
-  auto [op0, op1, op2, op3] = operands;
-
-  if (op3 == CONST0_RTX (<WVEC_HALF>mode))
-    emit_insn (
-      gen_<simd_isa>_<x>vmulwev_<simdfmt_w>_<simdfmt><u> (op0, op1, op2));
+  rtx (*gen4) (rtx, rtx, rtx, rtx);
+  if (operands[3] == CONST0_RTX (<WVEC_HALF>mode))
+    {
+      rtx (*gen3) (rtx, rtx, rtx)
+	= gen_<simd_isa>_<x>vmulwev_<simdfmt_w>_<simdfmt><u>;
+      emit_insn (gen3 (operands[0], operands[1], operands[2]));
+    }
   else
-    emit_insn (
-      gen_<simd_isa>_<x>vmaddwev_<simdfmt_w>_<simdfmt><u> (op0, op3, op1,
-							   op2));
+    {
+      gen4 = gen_<simd_isa>_<x>vmaddwev_<simdfmt_w>_<simdfmt><u>;
+      emit_insn (gen4 (operands[0], operands[1], operands[2], operands[3]));
+    }
 
-  emit_insn (
-    gen_<simd_isa>_<x>vmaddwod_<simdfmt_w>_<simdfmt><u> (op0, op0, op1, op2));
+  gen4 = gen_<simd_isa>_<x>vmaddwod_<simdfmt_w>_<simdfmt><u>;
+  emit_insn (gen4 (operands[0], operands[1], operands[2], operands[3]));
   DONE;
 })