diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index 647e89afb6a..ba8df6a7979 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -1466,8 +1466,16 @@ (define_predicate "fpmask_comparison_operator" ;; Return 1 if OP is a comparison operator suitable for vector/scalar ;; comparisons that generate a 0/-1 mask (i.e. the inverse of ;; fpmask_comparison_operator). +;; +;; invert_fpmask_comparison_operator is used to form floating point conditional +;; moves on power9. The instructions that would be generated (xscmpeqdp, +;; xscmpgtdp, or xscmpgedp) will raise an error if one of the arguments is a +;; signalling NaN. Don't allow the test to be inverted if NaNs are supported +;; and the comparison is an ordered comparison. (define_predicate "invert_fpmask_comparison_operator" - (match_code "ne,unlt,unle")) + (ior (match_code "ne") + (and (match_code "unlt,unle") + (match_test "flag_finite_math_only")))) ;; Return 1 if OP is a comparison operation suitable for integer vector/scalar ;; comparisons that generate a -1/0 mask. diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h index 4619142d197..ea9f267bb8e 100644 --- a/gcc/config/rs6000/rs6000-protos.h +++ b/gcc/config/rs6000/rs6000-protos.h @@ -114,8 +114,23 @@ extern const char *rs6000_sibcall_template (rtx *, unsigned int); extern const char *rs6000_indirect_call_template (rtx *, unsigned int); extern const char *rs6000_indirect_sibcall_template (rtx *, unsigned int); extern const char *rs6000_pltseq_template (rtx *, int); + +/* Whether we can reverse the sense of an ordered (UNLT, UNLE, UNGT, UNGE, + UNEQ, or LTGT) comairson. If we are doing floating point conditional moves + on power9 and above, we cannot convert an ordered comparison to unordered, + since the instructions (XSCMP{EQ,GT,GE}DP) that are used for conditional + moves can trap if an argument is a signalling NaN. However for normal jumps + we can reverse a comparison since we only use unordered compare instructions + which do not trap on signalling NaNs. */ + +enum reverse_cond_t { + REVERSE_COND_ORDERED_OK, + REVERSE_COND_NO_ORDERED +}; + extern enum rtx_code rs6000_reverse_condition (machine_mode, - enum rtx_code); + enum rtx_code, + enum reverse_cond_t); extern rtx rs6000_emit_eqne (machine_mode, rtx, rtx, rtx); extern rtx rs6000_emit_fp_cror (rtx_code, machine_mode, rtx); extern void rs6000_emit_sCOND (machine_mode, rtx[]); diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index f9f9a0b931d..c2235d917ad 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -15360,17 +15360,38 @@ rs6000_print_patchable_function_entry (FILE *file, } enum rtx_code -rs6000_reverse_condition (machine_mode mode, enum rtx_code code) +rs6000_reverse_condition (machine_mode mode, + enum rtx_code code, + enum reverse_cond_t ordered_cmp_ok) { /* Reversal of FP compares takes care -- an ordered compare - becomes an unordered compare and vice versa. */ - if (mode == CCFPmode - && (!flag_finite_math_only - || code == UNLT || code == UNLE || code == UNGT || code == UNGE - || code == UNEQ || code == LTGT)) - return reverse_condition_maybe_unordered (code); - else - return reverse_condition (code); + becomes an unordered compare and vice versa. + + However, this is not safe for ordered comparisons (i.e. for isgreater, + etc.) starting with the power9 because ifcvt.cc will want to create a fp + cmove, and the x{s,v}cmp{eq,gt,ge}{dp,qp} instructions will trap if one of + the arguments is a signalling NaN. */ + + if (mode == CCFPmode) + { + /* If NaNs are allowed, don't allow the reversal of floating point + comparisons when the comparison is used in the context of a floating + point conditional move when REVERSE_COND_NO_ORDERED is passed. We do + allow the comparsion to be reversed for explicit jumps when + REVERSE_COND_ORDERED_OK is passed. */ + if (!flag_finite_math_only) + return (ordered_cmp_ok == REVERSE_COND_NO_ORDERED + ? UNKNOWN + : reverse_condition_maybe_unordered (code)); + + /* Explicit ordered comparisions can be reversed if NaNs are not + allowed. */ + else if (code == UNLT || code == UNLE || code == UNGT || code == UNGE + || code == UNEQ || code == LTGT) + return reverse_condition_maybe_unordered (code); + } + + return reverse_condition (code); } /* Check if C (as 64bit integer) can be rotated to a constant which constains @@ -15980,11 +16001,14 @@ rs6000_emit_sCOND (machine_mode mode, rtx operands[]) rtx not_result = gen_reg_rtx (CCEQmode); rtx not_op, rev_cond_rtx; machine_mode cc_mode; + enum rtx_code rev; cc_mode = GET_MODE (XEXP (condition_rtx, 0)); - rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code), - SImode, XEXP (condition_rtx, 0), const0_rtx); + rev = rs6000_reverse_condition (cc_mode, cond_code, + REVERSE_COND_ORDERED_OK); + rev_cond_rtx = gen_rtx_fmt_ee (rev, SImode, XEXP (condition_rtx, 0), + const0_rtx); not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx); emit_insn (gen_rtx_SET (not_result, not_op)); condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx); diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index ec08c96d0f6..c595d7138bc 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -1812,11 +1812,17 @@ extern scalar_int_mode rs6000_pmode; /* Can the condition code MODE be safely reversed? This is safe in all cases on this port, because at present it doesn't use the - trapping FP comparisons (fcmpo). */ + trapping FP comparisons (fcmpo). + + However, this is not safe for ordered comparisons (i.e. for isgreater, etc.) + starting with the power9 because ifcvt.cc will want to create a fp cmove, + and the x{s,v}cmp{eq,gt,ge}{dp,qp} instructions will trap if one of the + arguments is a signalling NaN. */ #define REVERSIBLE_CC_MODE(MODE) 1 /* Given a condition code and a mode, return the inverse condition. */ -#define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE) +#define REVERSE_CONDITION(CODE, MODE) \ + rs6000_reverse_condition (MODE, CODE, REVERSE_COND_NO_ORDERED) /* Target cpu costs. */ diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 65da0c65330..5f7ff36617d 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -13497,7 +13497,7 @@ (define_insn "@cceq_rev_compare_" ;; If we are comparing the result of two comparisons, this can be done ;; using creqv or crxor. -(define_insn_and_split "" +(define_insn_and_split "*reverse_branch_comparison" [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y") (compare:CCEQ (match_operator 1 "branch_comparison_operator" [(match_operand 2 "cc_reg_operand" "y") @@ -13519,19 +13519,25 @@ (define_insn_and_split "" GET_MODE (operands[3])); if (! positive_1) - operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]), - GET_CODE (operands[1])), - SImode, - operands[2], const0_rtx); + { + enum rtx_code rev = rs6000_reverse_condition (GET_MODE (operands[2]), + GET_CODE (operands[1]), + REVERSE_COND_ORDERED_OK); + gcc_assert (rev != UNKNOWN); + operands[1] = gen_rtx_fmt_ee (rev, SImode, operands[2], const0_rtx); + } else if (GET_MODE (operands[1]) != SImode) operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode, operands[2], const0_rtx); if (! positive_2) - operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]), - GET_CODE (operands[3])), - SImode, - operands[4], const0_rtx); + { + enum rtx_code rev = rs6000_reverse_condition (GET_MODE (operands[4]), + GET_CODE (operands[3]), + REVERSE_COND_ORDERED_OK); + gcc_assert (rev != UNKNOWN); + operands[3] = gen_rtx_fmt_ee (rev, SImode, operands[4], const0_rtx); + } else if (GET_MODE (operands[3]) != SImode) operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode, operands[4], const0_rtx); diff --git a/gcc/testsuite/gcc.target/powerpc/pr118541-1.c b/gcc/testsuite/gcc.target/powerpc/pr118541-1.c new file mode 100644 index 00000000000..d5690dd7e38 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr118541-1.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-mdejagnu-cpu=power9 -O2" } */ +/* { dg-require-effective-target powerpc_vsx } */ + +/* PR target/118541 says that the ordered comparison functions like isgreater + should not optimize floating point conditional moves to use + x{s,v}cmp{eq,gt,ge}{dp,qp} and xxsel since that instruction can cause traps + if one of the arguments is a signaling NaN. */ + +/* Verify isgreater does not generate xscmpgtdp when NaNs are allowed. */ + +double +ordered_compare (double a, double b, double c, double d) +{ + /* + * fcmpu 0,1,2 + * fmr 1,4 + * bnglr 0 + * fmr 1,3 + * blr + */ + + return __builtin_isgreater (a, b) ? c : d; +} + +/* { dg-final { scan-assembler-not {\mxscmpg[te]dp\M} } } */ +/* { dg-final { scan-assembler-not {\mxxsel\M} } } */ +/* { dg-final { scan-assembler {\mxscmpudp\M|\mfcmpu\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr118541-2.c b/gcc/testsuite/gcc.target/powerpc/pr118541-2.c new file mode 100644 index 00000000000..5e1d83daeda --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr118541-2.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-mdejagnu-cpu=power9 -Ofast" } */ +/* { dg-require-effective-target powerpc_vsx } */ + +/* PR target/118541 says that the ordered comparison functions like isgreater + should not optimize floating point conditional moves to use + x{s,v}cmp{eq,gt,ge}{dp,qp} and xxsel since that instruction can cause traps + if one of the arguments is a signaling NaN. */ + +/* Verify isgreater does generate xscmpgtdp when NaNs are not allowed. */ + +double +ordered_compare (double a, double b, double c, double d) +{ + /* + * xscmpgtdp 1,1,2 + * xxsel 1,4,3,1 + * blr + */ + + return __builtin_isgreater (a, b) ? c : d; +} + +/* { dg-final { scan-assembler {\mxscmpg[te]dp\M} } } */ +/* { dg-final { scan-assembler {\mxxsel\M} } } */ +/* { dg-final { scan-assembler-not {\mxscmpudp\M|\mfcmpu\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr118541-3.c b/gcc/testsuite/gcc.target/powerpc/pr118541-3.c new file mode 100644 index 00000000000..bac7486d211 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr118541-3.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-mdejagnu-cpu=power9 -O2" } */ +/* { dg-require-effective-target powerpc_vsx } */ + +/* PR target/118541 says that the ordered comparison functions like isgreater + should not optimize floating point conditional moves to use + x{s,v}cmp{eq,gt,ge}{dp,qp} and xxsel since that instruction can cause traps + if one of the arguments is a signaling NaN. */ + +/* Verify normal > does generate xscmpgtdp when NaNs are allowed. */ + +double +normal_compare (double a, double b, double c, double d) +{ + /* + * xscmpgtdp 1,1,2 + * xxsel 1,4,3,1 + * blr + */ + + return a > b ? c : d; +} + +/* { dg-final { scan-assembler {\mxscmpg[te]dp\M} } } */ +/* { dg-final { scan-assembler {\mxxsel\M} } } */ +/* { dg-final { scan-assembler-not {\mxscmpudp\M|\mfcmpu\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr118541-4.c b/gcc/testsuite/gcc.target/powerpc/pr118541-4.c new file mode 100644 index 00000000000..3e82a937c7b --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr118541-4.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-mdejagnu-cpu=power9 -Ofast" } */ +/* { dg-require-effective-target powerpc_vsx } */ + +/* PR target/118541 says that the ordered comparison functions like isgreater + should not optimize floating point conditional moves to use + x{s,v}cmp{eq,gt,ge}{dp,qp} and xxsel since that instruction can cause traps + if one of the arguments is a signaling NaN. */ + +/* Verify normal > does generate xscmpgtdp when NaNs are not allowed. */ + +double +normal_compare (double a, double b, double c, double d) +{ + /* + * xscmpgtdp 1,1,2 + * xxsel 1,4,3,1 + * blr + */ + + return a > b ? c : d; +} + +/* { dg-final { scan-assembler {\mxscmpg[te]dp\M} } } */ +/* { dg-final { scan-assembler {\mxxsel\M} } } */ +/* { dg-final { scan-assembler-not {\mxscmpudp\M|\mfcmpu\M} } } */