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Message-ID: Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , "Kewen.Lin" , David Edelsohn , Peter Bergner , Will Schmidt References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-TM-AS-GCONF: 00 X-Proofpoint-GUID: NcHYd5e0adEOw6qvzpQidpnF6Xh7QcoE X-Proofpoint-ORIG-GUID: mvKphj2gR0eiKHLSLNmABGJEp0d3x_hE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.517,FMLib:17.11.64.514 definitions=2022-06-06_07,2022-06-03_01,2022-02-23_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 priorityscore=1501 impostorscore=0 lowpriorityscore=0 phishscore=0 bulkscore=0 mlxscore=0 spamscore=0 mlxlogscore=999 clxscore=1015 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2204290000 definitions=main-2206070000 X-Spam-Status: No, score=-10.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_MANYTO, KAM_SHORT, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Michael Meissner via Gcc-patches From: Michael Meissner Reply-To: Michael Meissner Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" [PATCH 3/3] Adjust MMA tests to account for no store vector pair. In changing the default for generating the store vector pair instructions, I had to adjust several of the MMA tests to remove checking for these instructions. Mostly I just deleted the scan-assembler lines checking for stxvp. In two of the tests, I added the -mstore-vector-pair option since the point of the test was to check for specific cases with store vector pair instructions. I have built bootstrap compilers and run the regression tests on three different systems: 1) Little endian power10 using the --with-cpu=power10 option. 2) Little endian power9 using the --with-cpu=power9 option. 3) Big endian power8 using the --with-cpu=power8 option. On this system, both 64-bit and 32-bit code generation was tested. There were no regressions in the runs. Can I check this patch into the trunk? If there are no changes needed for the backports, can I check this code into the active branches after a burn-in period? 2022-06-06 Michael Meissner gcc/testsuite/ * gcc.target/powerpc/mma-builtin-1.c: Eliminate checking for store vector pair instructions. * gcc.target/powerpc/mma-builtin-10-pair.c: Likewise. * gcc.target/powerpc/mma-builtin-10-quit.c: Likewise. * gcc.target/powerpc/mma-builtin-2.c: Likewise. * gcc.target/powerpc/mma-builtin-3.c: Likewise. * gcc.target/powerpc/mma-builtin-4.c: Likewise. * gcc.target/powerpc/mma-builtin-5.c: Likewise. * gcc.target/powerpc/mma-builtin-6.c: Likewise. * gcc.target/powerpc/mma-builtin-7.c: Likewise. * gcc.target/powerpc/mma-builtin-9.c: Likewise. * gcc.target/powerpc/mma-builtin-8.c: Add -mstore-vector-pair. * gcc.target/powerpc/pr102976.c: Likewise. --- gcc/testsuite/gcc.target/powerpc/mma-builtin-1.c | 1 - gcc/testsuite/gcc.target/powerpc/mma-builtin-10-pair.c | 2 -- gcc/testsuite/gcc.target/powerpc/mma-builtin-10-quad.c | 2 -- gcc/testsuite/gcc.target/powerpc/mma-builtin-2.c | 1 - gcc/testsuite/gcc.target/powerpc/mma-builtin-3.c | 1 - gcc/testsuite/gcc.target/powerpc/mma-builtin-4.c | 2 -- gcc/testsuite/gcc.target/powerpc/mma-builtin-5.c | 2 -- gcc/testsuite/gcc.target/powerpc/mma-builtin-6.c | 1 - gcc/testsuite/gcc.target/powerpc/mma-builtin-7.c | 2 -- gcc/testsuite/gcc.target/powerpc/mma-builtin-8.c | 2 +- gcc/testsuite/gcc.target/powerpc/mma-builtin-9.c | 2 -- gcc/testsuite/gcc.target/powerpc/pr102976.c | 6 +++++- 12 files changed, 6 insertions(+), 18 deletions(-) diff --git a/gcc/testsuite/gcc.target/powerpc/mma-builtin-1.c b/gcc/testsuite/gcc.target/powerpc/mma-builtin-1.c index 69ee826e1be..47b45b00403 100644 --- a/gcc/testsuite/gcc.target/powerpc/mma-builtin-1.c +++ b/gcc/testsuite/gcc.target/powerpc/mma-builtin-1.c @@ -260,7 +260,6 @@ foo13b (__vector_quad *dst, __vector_quad *src, vec_t *vec) /* { dg-final { scan-assembler-times {\mlxv\M} 40 } } */ /* { dg-final { scan-assembler-times {\mlxvp\M} 12 } } */ -/* { dg-final { scan-assembler-times {\mstxvp\M} 40 } } */ /* { dg-final { scan-assembler-times {\mxxmfacc\M} 20 } } */ /* { dg-final { scan-assembler-times {\mxxmtacc\M} 6 } } */ /* { dg-final { scan-assembler-times {\mxvbf16ger2\M} 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/mma-builtin-10-pair.c b/gcc/testsuite/gcc.target/powerpc/mma-builtin-10-pair.c index d8748d8e7d0..9522673d83e 100644 --- a/gcc/testsuite/gcc.target/powerpc/mma-builtin-10-pair.c +++ b/gcc/testsuite/gcc.target/powerpc/mma-builtin-10-pair.c @@ -16,6 +16,4 @@ foo (__vector_pair *dst, vec_t *src) } /* { dg-final { scan-assembler-not {\mlxv\M} } } */ -/* { dg-final { scan-assembler-not {\mstxv\M} } } */ /* { dg-final { scan-assembler-times {\mlxvp\M} 1 } } */ -/* { dg-final { scan-assembler-times {\mstxvp\M} 2 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/mma-builtin-10-quad.c b/gcc/testsuite/gcc.target/powerpc/mma-builtin-10-quad.c index 02342c76f5f..3cbdffc15ba 100644 --- a/gcc/testsuite/gcc.target/powerpc/mma-builtin-10-quad.c +++ b/gcc/testsuite/gcc.target/powerpc/mma-builtin-10-quad.c @@ -16,8 +16,6 @@ foo (__vector_quad *dst, vec_t *src) } /* { dg-final { scan-assembler-not {\mlxv\M} } } */ -/* { dg-final { scan-assembler-not {\mstxv\M} } } */ /* { dg-final { scan-assembler-times {\mlxvp\M} 4 } } */ /* { dg-final { scan-assembler-times {\mxxmtacc\M} 2 } } */ /* { dg-final { scan-assembler-times {\mxxmfacc\M} 2 } } */ -/* { dg-final { scan-assembler-times {\mstxvp\M} 4 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/mma-builtin-2.c b/gcc/testsuite/gcc.target/powerpc/mma-builtin-2.c index 0230d727657..5943702d8f3 100644 --- a/gcc/testsuite/gcc.target/powerpc/mma-builtin-2.c +++ b/gcc/testsuite/gcc.target/powerpc/mma-builtin-2.c @@ -59,7 +59,6 @@ foo3 (__vector_quad *dst, __vector_quad *src, vec_t *vec, __vector_pair *pvecp) /* { dg-final { scan-assembler-times {\mxxmtacc\M} 2 } } */ /* { dg-final { scan-assembler-times {\mlxv\M} 4 } } */ /* { dg-final { scan-assembler-times {\mlxvp\M} 8 } } */ -/* { dg-final { scan-assembler-times {\mstxvp\M} 8 } } */ /* { dg-final { scan-assembler-times {\mxvf64ger\M} 1 } } */ /* { dg-final { scan-assembler-times {\mxvf64gerpp\M} 1 } } */ /* { dg-final { scan-assembler-times {\mxvf64gerpn\M} 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/mma-builtin-3.c b/gcc/testsuite/gcc.target/powerpc/mma-builtin-3.c index 9bec78d333f..ee65ef9d96f 100644 --- a/gcc/testsuite/gcc.target/powerpc/mma-builtin-3.c +++ b/gcc/testsuite/gcc.target/powerpc/mma-builtin-3.c @@ -26,6 +26,5 @@ foo1 (vec_t *vec) /* { dg-final { scan-assembler-times {\mlxv\M} 2 } } */ /* { dg-final { scan-assembler-times {\mstxv\M} 2 } } */ /* { dg-final { scan-assembler-not {\mlxvp\M} } } */ -/* { dg-final { scan-assembler-not {\mstxvp\M} } } */ /* { dg-final { scan-assembler-times {\mxvcvspbf16\M} 1 } } */ /* { dg-final { scan-assembler-times {\mxvcvbf16spn\M} 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/mma-builtin-4.c b/gcc/testsuite/gcc.target/powerpc/mma-builtin-4.c index a9fb0107d12..aa6e6136f4f 100644 --- a/gcc/testsuite/gcc.target/powerpc/mma-builtin-4.c +++ b/gcc/testsuite/gcc.target/powerpc/mma-builtin-4.c @@ -68,6 +68,4 @@ bar2 (vec_t *dst, __vector_pair *src) /* { dg-final { scan-assembler-times {\mlxv\M} 6 } } */ /* { dg-final { scan-assembler-times {\mlxvp\M} 2 } } */ -/* { dg-final { scan-assembler-times {\mstxv\M} 4 } } */ -/* { dg-final { scan-assembler-times {\mstxvp\M} 3 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/mma-builtin-5.c b/gcc/testsuite/gcc.target/powerpc/mma-builtin-5.c index 00503b7343d..0d332acee93 100644 --- a/gcc/testsuite/gcc.target/powerpc/mma-builtin-5.c +++ b/gcc/testsuite/gcc.target/powerpc/mma-builtin-5.c @@ -41,7 +41,5 @@ bar (vec_t *dst, __vector_quad *src) /* { dg-final { scan-assembler-times {\mlxv\M} 8 } } */ /* { dg-final { scan-assembler-times {\mlxvp\M} 2 } } */ -/* { dg-final { scan-assembler-times {\mstxv\M} 4 } } */ -/* { dg-final { scan-assembler-times {\mstxvp\M} 4 } } */ /* { dg-final { scan-assembler-times {\mxxmfacc\M} 3 } } */ /* { dg-final { scan-assembler-times {\mxxmtacc\M} 3 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/mma-builtin-6.c b/gcc/testsuite/gcc.target/powerpc/mma-builtin-6.c index 715b28138e9..2f5747da070 100644 --- a/gcc/testsuite/gcc.target/powerpc/mma-builtin-6.c +++ b/gcc/testsuite/gcc.target/powerpc/mma-builtin-6.c @@ -17,4 +17,3 @@ foo (__vector_quad *dst) /* { dg-final { scan-assembler-not {\mxxmtacc\M} } } */ /* { dg-final { scan-assembler-times {\mxxsetaccz\M} 2 } } */ /* { dg-final { scan-assembler-times {\mxxmfacc\M} 2 } } */ -/* { dg-final { scan-assembler-times {\mstxvp\M} 4 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/mma-builtin-7.c b/gcc/testsuite/gcc.target/powerpc/mma-builtin-7.c index c661a4b84bc..6eba0a34e8a 100644 --- a/gcc/testsuite/gcc.target/powerpc/mma-builtin-7.c +++ b/gcc/testsuite/gcc.target/powerpc/mma-builtin-7.c @@ -19,8 +19,6 @@ foo (__vector_pair *dst, __vector_pair *src, long idx) #endif /* { dg-final { scan-assembler-not {\mlxv\M} } } */ -/* { dg-final { scan-assembler-not {\mstxv\M} } } */ /* { dg-final { scan-assembler-times {\mlxvp\M} 3 } } */ /* { dg-final { scan-assembler-times {\mlxvpx\M} 1 } } */ /* { dg-final { scan-assembler-times {\mplxvp\M} 1 } } */ -/* { dg-final { scan-assembler-times {\mstxvp\M} 5 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/mma-builtin-8.c b/gcc/testsuite/gcc.target/powerpc/mma-builtin-8.c index af29e479f83..cbd2e6dbae1 100644 --- a/gcc/testsuite/gcc.target/powerpc/mma-builtin-8.c +++ b/gcc/testsuite/gcc.target/powerpc/mma-builtin-8.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target power10_ok } */ -/* { dg-options "-mdejagnu-cpu=power10 -O2" } */ +/* { dg-options "-mdejagnu-cpu=power10 -O2 -mstore-vector-pair" } */ void foo (__vector_pair *dst, __vector_pair *src, long idx) diff --git a/gcc/testsuite/gcc.target/powerpc/mma-builtin-9.c b/gcc/testsuite/gcc.target/powerpc/mma-builtin-9.c index 397d0f1db35..7232e840204 100644 --- a/gcc/testsuite/gcc.target/powerpc/mma-builtin-9.c +++ b/gcc/testsuite/gcc.target/powerpc/mma-builtin-9.c @@ -23,6 +23,4 @@ bar (__vector_quad *dst, vec_t *src) } /* { dg-final { scan-assembler-not {\mlxv\M} } } */ -/* { dg-final { scan-assembler-not {\mstxv\M} } } */ /* { dg-final { scan-assembler-times {\mlxvp\M} 3 } } */ -/* { dg-final { scan-assembler-times {\mstxvp\M} 3 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr102976.c b/gcc/testsuite/gcc.target/powerpc/pr102976.c index 5a4320f8e0a..c975eba86da 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr102976.c +++ b/gcc/testsuite/gcc.target/powerpc/pr102976.c @@ -1,7 +1,11 @@ /* { dg-require-effective-target power10_ok } */ -/* { dg-options "-O2 -mdejagnu-cpu=power10" } */ +/* { dg-options "-O2 -mdejagnu-cpu=power10 -mstore-vector-pair" } */ #include + +/* The test relies on store vector pair being generated. Otherwise, it + will generate 2 stxv instructions. */ + void bug (__vector_pair *dst) {