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Fri, 13 May 2022 16:19:53 +0000 (GMT) Date: Fri, 13 May 2022 12:19:52 -0400 To: gcc-patches@gcc.gnu.org, Michael Meissner , Segher Boessenkool , "Kewen.Lin" , David Edelsohn , Peter Bergner , Will Schmidt Subject: [PATCH] Generate vadduqm and vsubuqm for TImode add/subtract Message-ID: Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , "Kewen.Lin" , David Edelsohn , Peter Bergner , Will Schmidt MIME-Version: 1.0 Content-Disposition: inline X-TM-AS-GCONF: 00 X-Proofpoint-GUID: ZftNmEW_GOgcMc0TNGamkDjUqjuZZJ_T X-Proofpoint-ORIG-GUID: e30fOhE04eGjMMPMPEDsYrknJ7NkKWNP X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.858,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-05-13_08,2022-05-13_01,2022-02-23_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxscore=0 suspectscore=0 bulkscore=0 adultscore=0 spamscore=0 clxscore=1015 phishscore=0 mlxlogscore=999 impostorscore=0 malwarescore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2202240000 definitions=main-2205130069 X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_MANYTO, KAM_SHORT, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Michael Meissner via Gcc-patches From: Michael Meissner Reply-To: Michael Meissner Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Generate vadduqm and vsubuqm for TImode add/subtract If the TImode variable is in an Altivec register instead of a GPR register, then generate vadduqm and vsubuqm instead of having to move the value to the GPR registers and doing the add and subtract with carry instructions. To do this, we have to delay the splitting of the addition and subtraction until after register allocation. I have built this patch on little endian power10, little endian power9, and big endian power8 systems. There were no regressions. Can I install this patch to the GCC 13 master branch? 2022-05-13 Michael Meissner gcc/ * config/rs6000/rs6000.md (addti3): Generate vadduqm if we are using the Altivec registers. (subti3): Generate vsubuqm if we using the Altivec registers. (negti3): New insn. gcc/testsuite/ * gcc.target/powerpc/vadduqm-vsubuqm.c: New test. --- gcc/config/rs6000/rs6000.md | 82 ++++++++++++++----- .../gcc.target/powerpc/vadduqm-vsubuqm.c | 22 +++++ 2 files changed, 83 insertions(+), 21 deletions(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/vadduqm-vsubuqm.c diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 83eacec57ba..f120ca0b48d 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -7139,15 +7139,22 @@ (define_expand "feraiseexceptsi" ;; ;; Addti3/subti3 are define_insn_and_splits instead of define_expand, to allow ;; for combine to make things like multiply and add with extend operations. +;; +;; Also add support in case the 128-bit integer happens to be an Altivec +;; register. (define_insn_and_split "addti3" - [(set (match_operand:TI 0 "gpc_reg_operand" "=&r,r,r") - (plus:TI (match_operand:TI 1 "gpc_reg_operand" "r, 0,r") - (match_operand:TI 2 "reg_or_short_operand" "rI,r,0"))) + [(set (match_operand:TI 0 "gpc_reg_operand" "=&r, r,r,v") + (plus:TI (match_operand:TI 1 "gpc_reg_operand" "r, 0,r,v") + (match_operand:TI 2 "reg_or_short_operand" "rI,r,0,v"))) (clobber (reg:DI CA_REGNO))] "TARGET_64BIT" - "#" - "&& 1" + "@ + # + # + # + vadduqm %0,%1,%2" + "&& reload_completed && int_reg_operand (operands[0], TImode)" [(pc)] { rtx lo0 = gen_lowpart (DImode, operands[0]); @@ -7157,27 +7164,27 @@ (define_insn_and_split "addti3" rtx hi1 = gen_highpart (DImode, operands[1]); rtx hi2 = gen_highpart_mode (DImode, TImode, operands[2]); - if (!reg_or_short_operand (lo2, DImode)) - lo2 = force_reg (DImode, lo2); - if (!adde_operand (hi2, DImode)) - hi2 = force_reg (DImode, hi2); - emit_insn (gen_adddi3_carry (lo0, lo1, lo2)); emit_insn (gen_adddi3_carry_in (hi0, hi1, hi2)); DONE; } - [(set_attr "length" "8") + [(set_attr "length" "8,8,8,*") + (set_attr "isa" "*,*,*,p8v") (set_attr "type" "add") (set_attr "size" "128")]) (define_insn_and_split "subti3" - [(set (match_operand:TI 0 "gpc_reg_operand" "=&r,r,r") - (minus:TI (match_operand:TI 1 "reg_or_short_operand" "rI,0,r") - (match_operand:TI 2 "gpc_reg_operand" "r, r,0"))) + [(set (match_operand:TI 0 "gpc_reg_operand" "=&r, r,r,v") + (minus:TI (match_operand:TI 1 "reg_or_short_operand" "rI,0,r,v") + (match_operand:TI 2 "gpc_reg_operand" "r, r,0,v"))) (clobber (reg:DI CA_REGNO))] "TARGET_64BIT" - "#" - "&& 1" + "@ + # + # + # + vsubuqm %0,%1,%2" + "&& reload_completed && int_reg_operand (operands[0], TImode)" [(pc)] { rtx lo0 = gen_lowpart (DImode, operands[0]); @@ -7187,16 +7194,49 @@ (define_insn_and_split "subti3" rtx hi1 = gen_highpart_mode (DImode, TImode, operands[1]); rtx hi2 = gen_highpart (DImode, operands[2]); - if (!reg_or_short_operand (lo1, DImode)) - lo1 = force_reg (DImode, lo1); - if (!adde_operand (hi1, DImode)) - hi1 = force_reg (DImode, hi1); - emit_insn (gen_subfdi3_carry (lo0, lo2, lo1)); emit_insn (gen_subfdi3_carry_in (hi0, hi2, hi1)); DONE; +} + [(set_attr "length" "8,8,8,*") + (set_attr "isa" "*,*,*,p8v") + (set_attr "type" "add") + (set_attr "size" "128")]) + +;; 128-bit integer negation, normally use GPRs. If we are using Altivec +;; registers, create a 0 and do a vsubuqm. +(define_insn_and_split "negti3" + [(set (match_operand:TI 0 "gpc_reg_operand" "=&r,&v") + (neg:TI (match_operand:TI 1 "gpc_reg_operand" "r,v"))) + (clobber (reg:DI CA_REGNO))] + "TARGET_64BIT" + "#" + "&& reload_completed" + [(pc)] +{ + rtx dest = operands[0]; + rtx src = operands[1]; + + if (altivec_register_operand (dest, TImode)) + { + emit_move_insn (dest, const0_rtx); + emit_insn (gen_subti3 (dest, dest, src)); + DONE; + } + else + { + rtx dest_lo = gen_lowpart (DImode, dest); + rtx dest_hi = gen_highpart (DImode, dest); + rtx src_lo = gen_lowpart (DImode, src); + rtx src_hi = gen_highpart (DImode, src); + + emit_insn (gen_subfdi3_carry (dest_lo, src_lo, const0_rtx)); + emit_insn (gen_subfdi3_carry_in (dest_hi, src_hi, const0_rtx)); + DONE; + } } [(set_attr "length" "8") + (set_attr "isa" "*,p8v") (set_attr "type" "add") (set_attr "size" "128")]) diff --git a/gcc/testsuite/gcc.target/powerpc/vadduqm-vsubuqm.c b/gcc/testsuite/gcc.target/powerpc/vadduqm-vsubuqm.c new file mode 100644 index 00000000000..5cb2fe37e9c --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vadduqm-vsubuqm.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target int128 } */ +/* { dg-options "-O2 -mdejagnu-cpu=power10" } */ +/* { dg-require-effective-target power10_ok } */ + +/* Test that we generate vadduqm and vsubuqm for 128-bit integer add and + subtracts if the value is in an Altivec register. We use 128-bit divide to + force the register selection to be in an altivec register. */ + +void +test (__int128_t *p, + __int128_t *q, + __int128_t *r, + __int128_t *s, + __int128_t *t) +{ + *p = (*q + *r) / (*s - *t); /* vadduqm, vsubuqm, vdivsq. */ +} + +/* { dg-final { scan-assembler {\mvadduqm\M} } } */ +/* { dg-final { scan-assembler {\mvdivsq\M} } } */ +/* { dg-final { scan-assembler {\mvsubuqm\M} } } */