diff mbox series

Replace UNSPEC with RTL code for extendditi2.

Message ID Yn5wnicjLicdy3+a@toto.the-meissners.org
State New
Headers
Series Replace UNSPEC with RTL code for extendditi2. |

Commit Message

Michael Meissner May 13, 2022, 2:52 p.m. UTC 
  Replace UNSPEC with RTL code for extendditi2.

When I submitted my patch on March 12th for extendditi2, Segher wished I
had removed the use of the UNSPEC for the vextsd2q instruction.  This
patch rewrites extendditi2_vector to use VEC_SELECT rather than UNSPEC.

2022-05-13   Michael Meissner  <meissner@linux.ibm.com>

gcc/
	* config/rs6000/vsx.md (UNSPEC_EXTENDDITI2): Delete.
	(extendditi2_vector): Rewrite to use VEC_SELECT as a
	define_expand.
	(extendditi2_vector2): New insn.
---
 gcc/config/rs6000/vsx.md | 22 ++++++++++++++++++----
 1 file changed, 18 insertions(+), 4 deletions(-)

Comments

will schmidt May 13, 2022, 5:29 p.m. UTC | #1 
On Fri, 2022-05-13 at 10:52 -0400, Michael Meissner wrote:
> Replace UNSPEC with RTL code for extendditi2.
> 

Hi,


> When I submitted my patch on March 12th for extendditi2, Segher
> wished I
> had removed the use of the UNSPEC for the vextsd2q instruction.  This
> patch rewrites extendditi2_vector to use VEC_SELECT rather than
> UNSPEC.


I'd suggest a paragraph break between the two sentences.   


> 
> 2022-05-13   Michael Meissner  <meissner@linux.ibm.com>
> 
> gcc/
> 	* config/rs6000/vsx.md (UNSPEC_EXTENDDITI2): Delete.

> 	(extendditi2_vector): Rewrite to use VEC_SELECT as a
> 	define_expand.

> 	(extendditi2_vector2): New insn.


Ok, so per my interpretation of the patch below, it converts the
define_insn extendditi2_vector into a define_expand, and creates a new
extendditi2_vector2 instruction.  


Content below seems reasonable, I've not reviewed it extensively.  

Thanks
-Will

> ---
>  gcc/config/rs6000/vsx.md | 22 ++++++++++++++++++----
>  1 file changed, 18 insertions(+), 4 deletions(-)
> 
> diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
> index a1a1ce95195..c091e5e2f47 100644
> --- a/gcc/config/rs6000/vsx.md
> +++ b/gcc/config/rs6000/vsx.md
> @@ -358,7 +358,6 @@ (define_c_enum "unspec"
>     UNSPEC_VSX_FIRST_MISMATCH_EOS_INDEX
>     UNSPEC_XXGENPCV
>     UNSPEC_MTVSBM
> -   UNSPEC_EXTENDDITI2
>     UNSPEC_VCNTMB
>     UNSPEC_VEXPAND
>     UNSPEC_VEXTRACT
> @@ -5083,10 +5082,25 @@ (define_insn_and_split "extendditi2"
>     (set_attr "type" "shift,load,vecmove,vecperm,load")])
> 
>  ;; Sign extend 64-bit value in TI reg, word 1, to 128-bit value in
> TI reg
> -(define_insn "extendditi2_vector"
> +(define_expand "extendditi2_vector"
> +  [(use (match_operand:TI 0 "gpc_reg_operand"))
> +   (use (match_operand:TI 1 "gpc_reg_operand"))]
> +  "TARGET_POWER10"
> +{
> +  rtx dest = operands[0];
> +  rtx src_v2di = gen_lowpart (V2DImode, operands[1]);
> +  rtx element = GEN_INT (VECTOR_ELEMENT_SCALAR_64BIT);
> +
> +  emit_insn (gen_extendditi2_vector2 (dest, src_v2di, element));
> +  DONE;
> +})
> +
> +(define_insn "extendditi2_vector2"
>    [(set (match_operand:TI 0 "gpc_reg_operand" "=v")
> -	(unspec:TI [(match_operand:TI 1 "gpc_reg_operand" "v")]
> -		     UNSPEC_EXTENDDITI2))]
> +	(sign_extend:TI
> +	 (vec_select:DI
> +	  (match_operand:V2DI 1 "gpc_reg_operand" "v")
> +	  (parallel [(match_operand 2 "vsx_scalar_64bit" "wD")]))))]
>    "TARGET_POWER10"
>    "vextsd2q %0,%1"
>    [(set_attr "type" "vecexts")])
> -- 
> 2.35.3
> 
>
diff mbox series

Patch

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index a1a1ce95195..c091e5e2f47 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -358,7 +358,6 @@  (define_c_enum "unspec"
    UNSPEC_VSX_FIRST_MISMATCH_EOS_INDEX
    UNSPEC_XXGENPCV
    UNSPEC_MTVSBM
-   UNSPEC_EXTENDDITI2
    UNSPEC_VCNTMB
    UNSPEC_VEXPAND
    UNSPEC_VEXTRACT
@@ -5083,10 +5082,25 @@  (define_insn_and_split "extendditi2"
    (set_attr "type" "shift,load,vecmove,vecperm,load")])
 
 ;; Sign extend 64-bit value in TI reg, word 1, to 128-bit value in TI reg
-(define_insn "extendditi2_vector"
+(define_expand "extendditi2_vector"
+  [(use (match_operand:TI 0 "gpc_reg_operand"))
+   (use (match_operand:TI 1 "gpc_reg_operand"))]
+  "TARGET_POWER10"
+{
+  rtx dest = operands[0];
+  rtx src_v2di = gen_lowpart (V2DImode, operands[1]);
+  rtx element = GEN_INT (VECTOR_ELEMENT_SCALAR_64BIT);
+
+  emit_insn (gen_extendditi2_vector2 (dest, src_v2di, element));
+  DONE;
+})
+
+(define_insn "extendditi2_vector2"
   [(set (match_operand:TI 0 "gpc_reg_operand" "=v")
-	(unspec:TI [(match_operand:TI 1 "gpc_reg_operand" "v")]
-		     UNSPEC_EXTENDDITI2))]
+	(sign_extend:TI
+	 (vec_select:DI
+	  (match_operand:V2DI 1 "gpc_reg_operand" "v")
+	  (parallel [(match_operand 2 "vsx_scalar_64bit" "wD")]))))]
   "TARGET_POWER10"
   "vextsd2q %0,%1"
   [(set_attr "type" "vecexts")])