From patchwork Mon Mar 28 16:28:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Meissner X-Patchwork-Id: 52421 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A2C7A3857C4D for ; Mon, 28 Mar 2022 16:29:42 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org A2C7A3857C4D DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1648484982; bh=imChlbuoiDn4fqhXHQVb+atrkelfySTHqLxmoDiJ3xo=; h=Date:To:Subject:References:In-Reply-To:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To: From; b=ghPJe4DoIpYhdYOn7Q7FxNWkqyv0ZYj8uajaNnbd/wNbAqOTjT1/hFrkloWMDimO+ +YO0IZLe9OOrrhophyFKrhD6c2sO7xD+/XJkogPKIzKS6jq46OlUH3hnOy5uRogmra 0qJTxZUYNdXQOfV8unydatA46+yOiAcxMC+Z19p8= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by sourceware.org (Postfix) with ESMTPS id 5F2763857C4D for ; Mon, 28 Mar 2022 16:29:03 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 5F2763857C4D Received: from pps.filterd (m0098409.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 22SFcfet017941; Mon, 28 Mar 2022 16:29:02 GMT Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com with ESMTP id 3f3fjm1ap3-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Mar 2022 16:29:02 +0000 Received: from m0098409.ppops.net (m0098409.ppops.net [127.0.0.1]) by pps.reinject (8.16.0.43/8.16.0.43) with SMTP id 22SGOLgN015204; Mon, 28 Mar 2022 16:29:01 GMT Received: from ppma02wdc.us.ibm.com (aa.5b.37a9.ip4.static.sl-reverse.com [169.55.91.170]) by mx0a-001b2d01.pphosted.com with ESMTP id 3f3fjm1ang-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Mar 2022 16:29:01 +0000 Received: from pps.filterd (ppma02wdc.us.ibm.com [127.0.0.1]) by ppma02wdc.us.ibm.com (8.16.1.2/8.16.1.2) with SMTP id 22SGHNSE018671; Mon, 28 Mar 2022 16:29:00 GMT Received: from b01cxnp23032.gho.pok.ibm.com (b01cxnp23032.gho.pok.ibm.com [9.57.198.27]) by ppma02wdc.us.ibm.com with ESMTP id 3f1tf96f64-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Mar 2022 16:29:00 +0000 Received: from b01ledav003.gho.pok.ibm.com (b01ledav003.gho.pok.ibm.com [9.57.199.108]) by b01cxnp23032.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 22SGT0jI26345976 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 28 Mar 2022 16:29:00 GMT Received: from b01ledav003.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id EC499B2068; Mon, 28 Mar 2022 16:28:59 +0000 (GMT) Received: from b01ledav003.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id ADCC1B2064; Mon, 28 Mar 2022 16:28:59 +0000 (GMT) Received: from toto.the-meissners.org (unknown [9.65.244.27]) by b01ledav003.gho.pok.ibm.com (Postfix) with ESMTPS; Mon, 28 Mar 2022 16:28:59 +0000 (GMT) Date: Mon, 28 Mar 2022 12:28:55 -0400 To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , David Edelsohn , Peter Bergner , Will Schmidt Subject: [PATCH 4/4] Allow vsx_extract_ to use Altivec registers, PR target/99293 Message-ID: Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , David Edelsohn , Peter Bergner , Will Schmidt References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: czMWVm7p8ha_nCpbH5VdWzJLnVbnzuy_ X-Proofpoint-GUID: hgvFcoSXobqu0oDc_pHd_cXtt_xmpV4t X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.850,Hydra:6.0.425,FMLib:17.11.64.514 definitions=2022-03-28_06,2022-03-28_01,2022-02-23_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 clxscore=1015 mlxlogscore=999 impostorscore=0 lowpriorityscore=0 spamscore=0 mlxscore=0 priorityscore=1501 suspectscore=0 phishscore=0 malwarescore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2202240000 definitions=main-2203280090 X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_NUMSUBJECT, RCVD_IN_MSPIKE_H5, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Michael Meissner via Gcc-patches From: Michael Meissner Reply-To: Michael Meissner Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Allow vsx_extract_ to use Altivec registers, PR target/99293 In looking at PR target/99293, I noticed that the vsx_extract_ pattern for V2DImode and V2DFmode only allowed traditional floating point registers, and it did not allow Altivec registers. The original code was written a few years ago when we used the old register allocator, and support for scalar floating point in Altivec registers was just being added to GCC. I have built the spec 2017 benchmark suite With all 4 patches in this series applied, and compared it to the build with the previous 3 patches applied. In addition to the changes from the previous 3 patches, this patch now changes the code for the following 3 benchmarks (2 floating point, 1 integer): bwaves_r, fotonik3d_r, xalancbmk_r I have built bootstrap versions on the following systems. There were no regressions in the runs: Power9 little endian, --with-cpu=power9 Power10 little endian, --with-cpu=power10 Power8 big endian, --with-cpu=power8 (both 32-bit & 64-bit tests) Can I install this into the trunk? After a burn-in period, can I backport and install this into GCC 11 and GCC 10 branches? 2022-03-28 Michael Meissner gcc/ PR target/99293 * config/rs6000/rs6000.md (vsx_extract_): Allow destination to be an Altivec register. --- gcc/config/rs6000/vsx.md | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 2a23807c2dc..d30fd4f2596 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -3397,15 +3397,12 @@ (define_expand "vsx_set_" ;; Optimize cases were we can do a simple or direct move. ;; Or see if we can avoid doing the move at all -;; There are some unresolved problems with reload that show up if an Altivec -;; register was picked. Limit the scalar value to FPRs for now. - (define_insn "vsx_extract_" - [(set (match_operand: 0 "gpc_reg_operand" "=d, d, wr, wr") + [(set (match_operand: 0 "gpc_reg_operand" "=wa, wa, wr, wr") (vec_select: - (match_operand:VSX_D 1 "gpc_reg_operand" "wa, wa, wa, wa") + (match_operand:VSX_D 1 "gpc_reg_operand" "wa, wa, wa, wa") (parallel - [(match_operand:QI 2 "const_0_to_1_operand" "wD, n, wD, n")])))] + [(match_operand:QI 2 "const_0_to_1_operand" "wD, n, wD, n")])))] "VECTOR_MEM_VSX_P (mode)" { int element = INTVAL (operands[2]);