From patchwork Fri Nov 19 14:55:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Meissner X-Patchwork-Id: 47936 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 97A3C3858038 for ; Fri, 19 Nov 2021 14:56:51 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 97A3C3858038 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1637333811; bh=amFPFZ7Tw3z9Fkf1atxkOGiH9N0eKpFBU6Jqz9zdj6k=; h=Date:To:Subject:References:In-Reply-To:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To: From; b=tB1WSHyupyzlDC8UtrhqA96SmKn+l2LfK354jDE4582IsptVRlKO1JD+fBwAyt6Qj 37nQCQ7BPz06UD5AJ/JmB1KojxjhydcNT4IHgbpx6tJQUQy+WIYvrQOSKWDFbBxy7I 6e/Dkmbe3+Dswb9BB8X3PAY1ucmKRdnpLPJS8XWs= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by sourceware.org (Postfix) with ESMTPS id CC0CD385800C for ; Fri, 19 Nov 2021 14:55:57 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org CC0CD385800C Received: from pps.filterd (m0098409.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 1AJEBsOR004294; Fri, 19 Nov 2021 14:55:55 GMT Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com with ESMTP id 3cec0kjtdf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 19 Nov 2021 14:55:55 +0000 Received: from m0098409.ppops.net (m0098409.ppops.net [127.0.0.1]) by pps.reinject (8.16.0.43/8.16.0.43) with SMTP id 1AJEm36G011521; Fri, 19 Nov 2021 14:55:55 GMT Received: from ppma02dal.us.ibm.com (a.bd.3ea9.ip4.static.sl-reverse.com [169.62.189.10]) by mx0a-001b2d01.pphosted.com with ESMTP id 3cec0kjtd7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 19 Nov 2021 14:55:55 +0000 Received: from pps.filterd (ppma02dal.us.ibm.com [127.0.0.1]) by ppma02dal.us.ibm.com (8.16.1.2/8.16.1.2) with SMTP id 1AJErC7d009894; Fri, 19 Nov 2021 14:55:54 GMT Received: from b03cxnp08026.gho.boulder.ibm.com (b03cxnp08026.gho.boulder.ibm.com [9.17.130.18]) by ppma02dal.us.ibm.com with ESMTP id 3ca50em1ds-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 19 Nov 2021 14:55:54 +0000 Received: from b03ledav002.gho.boulder.ibm.com (b03ledav002.gho.boulder.ibm.com [9.17.130.233]) by b03cxnp08026.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 1AJEtqGs59310450 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 19 Nov 2021 14:55:53 GMT Received: from b03ledav002.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C882C13605E; Fri, 19 Nov 2021 14:55:52 +0000 (GMT) Received: from b03ledav002.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 4D105136055; Fri, 19 Nov 2021 14:55:52 +0000 (GMT) Received: from toto.the-meissners.org (unknown [9.65.240.210]) by b03ledav002.gho.boulder.ibm.com (Postfix) with ESMTPS; Fri, 19 Nov 2021 14:55:52 +0000 (GMT) Date: Fri, 19 Nov 2021 09:55:50 -0500 To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , David Edelsohn , Bill Schmidt , Peter Bergner , Will Schmidt Subject: [PATCH 2/3] Set power10 fusion if -mtune=power10. Message-ID: Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , David Edelsohn , Bill Schmidt , Peter Bergner , Will Schmidt References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: L8IwzSj543JFmvOd9TU7_X6eMxMvzm6R X-Proofpoint-GUID: JuVoPXlRD7Uyyuf_p0Uwh4951DZBUeTt X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-11-19_09,2021-11-17_01,2020-04-07_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 priorityscore=1501 bulkscore=0 lowpriorityscore=0 clxscore=1015 spamscore=0 impostorscore=0 mlxscore=0 mlxlogscore=999 phishscore=0 malwarescore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2110150000 definitions=main-2111190081 X-Spam-Status: No, score=-10.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_MANYTO, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Michael Meissner via Gcc-patches From: Michael Meissner Reply-To: Michael Meissner Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Set power10 fusion if -mtune=power10. In doing the patch for zero cycle moves for switch statements and indirect jumps, I noticed the fusion support is only done if -mcpu=power10. This option enables power10 fusion if we use -mtune=power10. I have built and run the testsuites on little endian power9 and power10 systems with no regressions. Can I install this patch? 2021-11-19 Michael Meissner * config/rs6000/rs6000.c (rs6000_option_override_internal): Enable power10 fusion if -mtune=power10. (rs6000_opt_masks): Add power10 fusion options. --- gcc/config/rs6000/rs6000.c | 25 +++++++++++++++++-------- 1 file changed, 17 insertions(+), 8 deletions(-) diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 6780304a5eb..8531cef0337 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -4469,35 +4469,36 @@ rs6000_option_override_internal (bool global_init_p) if (TARGET_POWER10 && (rs6000_isa_flags_explicit & OPTION_MASK_MMA) == 0) rs6000_isa_flags |= OPTION_MASK_MMA; - if (TARGET_POWER10 + /* Enable power10 tuning if either -mcpu=power10 or -mtune=power10. */ + if ((TARGET_POWER10 || rs6000_tune == PROCESSOR_POWER10) && (rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION) == 0) rs6000_isa_flags |= OPTION_MASK_P10_FUSION; - if (TARGET_POWER10 && + if (TARGET_P10_FUSION && (rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION_LD_CMPI) == 0) rs6000_isa_flags |= OPTION_MASK_P10_FUSION_LD_CMPI; - if (TARGET_POWER10 + if (TARGET_P10_FUSION && (rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION_2LOGICAL) == 0) rs6000_isa_flags |= OPTION_MASK_P10_FUSION_2LOGICAL; - if (TARGET_POWER10 + if (TARGET_P10_FUSION && (rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION_LOGADD) == 0) rs6000_isa_flags |= OPTION_MASK_P10_FUSION_LOGADD; - if (TARGET_POWER10 + if (TARGET_P10_FUSION && (rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION_ADDLOG) == 0) rs6000_isa_flags |= OPTION_MASK_P10_FUSION_ADDLOG; - if (TARGET_POWER10 + if (TARGET_P10_FUSION && (rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION_2ADD) == 0) rs6000_isa_flags |= OPTION_MASK_P10_FUSION_2ADD; - if (TARGET_POWER10 + if (TARGET_P10_FUSION && (rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION_2STORE) == 0) rs6000_isa_flags |= OPTION_MASK_P10_FUSION_2STORE; - if (TARGET_POWER10 + if (TARGET_P10_FUSION && (rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION_ZERO_CYCLE) == 0) rs6000_isa_flags |= OPTION_MASK_P10_FUSION_ZERO_CYCLE; @@ -24292,6 +24293,14 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] = { "power9-misc", OPTION_MASK_P9_MISC, false, true }, { "power9-vector", OPTION_MASK_P9_VECTOR, false, true }, { "power10-fusion", OPTION_MASK_P10_FUSION, false, true }, + { "power10-fusion-ld-cmpi", OPTION_MASK_P10_FUSION_LD_CMPI, false, true }, + { "power10-fusion-2logical", OPTION_MASK_P10_FUSION_2LOGICAL,false, true }, + { "power10-fusion-logical-add", OPTION_MASK_P10_FUSION_LOGADD,false, true }, + { "power10-fusion-add-logical", OPTION_MASK_P10_FUSION_ADDLOG,false, true }, + { "power10-fusion-2add", OPTION_MASK_P10_FUSION_2ADD, false, true }, + { "power10-fusion-2store", OPTION_MASK_P10_FUSION_2STORE, false, true }, + { "power10-fusion-zero-cycle", OPTION_MASK_P10_FUSION_ZERO_CYCLE, + false, true }, { "powerpc-gfxopt", OPTION_MASK_PPC_GFXOPT, false, true }, { "powerpc-gpopt", OPTION_MASK_PPC_GPOPT, false, true }, { "prefixed", OPTION_MASK_PREFIXED, false, true },