[8] PowerPC: Support load/store vector with right length.
Commit Message
This patch adds support for new instructions that may be added to the PowerPC
architecture in the future to enhance the load and store vector with length
instructions.
The current instructions (lxvl, lxvll, stxvl, and stxvll) are inconvient to use
since the count for the number of bytes must be in the top 8 bits of the GPR
register, instead of the bottom 8 bits. This meant that code generating these
instructions typically had to do a shift left by 56 bits to get the count into
the right position. In a future version of the PowerPC architecture, new
variants of these instructions might be added that expect the count to be in
the bottom 8 bits of the GPR register. These patches add this support to GCC
if the user uses the -mcpu=future option.
I tested this patch on a little endian power10 system with long double using
the tradiational IBM double double format. Assuming the other 6 patches for
-mcpu=future are checked in (or at least the first two patches), can I check
this patch into the master branch for GCC 13.
2022-11-11 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (lxvl): If -mcpu=future, generate the lxvl with
the shift count automaticaly used in the insn.
(lxvrl): New insn for -mcpu=future.
(lxvrll): Likewise.
(stxvl): If -mcpu=future, generate the stxvl with the shift count
automaticaly used in the insn.
(stxvrl): New insn for -mcpu=future.
(stxvrll): Likewise.
gcc/testsuite/
* gcc.target/powerpc/lxvrl.c: New test.
---
gcc/config/rs6000/vsx.md | 122 +++++++++++++++++++----
gcc/testsuite/gcc.target/powerpc/lxvrl.c | 31 ++++++
2 files changed, 132 insertions(+), 21 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/powerpc/lxvrl.c
Comments
Ping patch. We really would like to get these possible future PowerPC insn
changes into GCC 13.
| Date: Sat, 12 Nov 2022 00:10:59 -0500
| Subject: [PATCH 8] PowerPC: Support load/store vector with right length.
| Message-ID: <Y28q48o93tWF223A@toto.the-meissners.org>
@@ -5582,20 +5582,32 @@ (define_expand "first_mismatch_or_eos_index_<mode>"
DONE;
})
-;; Load VSX Vector with Length
+;; Load VSX Vector with Length. If we have lxvrl, we don't have to do an
+;; explicit shift left into a pseudo.
(define_expand "lxvl"
- [(set (match_dup 3)
- (ashift:DI (match_operand:DI 2 "register_operand")
- (const_int 56)))
- (set (match_operand:V16QI 0 "vsx_register_operand")
- (unspec:V16QI
- [(match_operand:DI 1 "gpc_reg_operand")
- (mem:V16QI (match_dup 1))
- (match_dup 3)]
- UNSPEC_LXVL))]
+ [(use (match_operand:V16QI 0 "vsx_register_operand"))
+ (use (match_operand:DI 1 "gpc_reg_operand"))
+ (use (match_operand:DI 2 "gpc_reg_operand"))]
"TARGET_P9_VECTOR && TARGET_64BIT"
{
- operands[3] = gen_reg_rtx (DImode);
+ rtx shift_len = gen_rtx_ASHIFT (DImode, operands[2], GEN_INT (56));
+ rtx len;
+
+ if (TARGET_FUTURE)
+ len = shift_len;
+ else
+ {
+ len = gen_reg_rtx (DImode);
+ emit_insn (gen_rtx_SET (len, shift_len));
+ }
+
+ rtx dest = operands[0];
+ rtx addr = operands[1];
+ rtx mem = gen_rtx_MEM (V16QImode, addr);
+ rtvec rv = gen_rtvec (3, addr, mem, len);
+ rtx lxvl = gen_rtx_UNSPEC (V16QImode, rv, UNSPEC_LXVL);
+ emit_insn (gen_rtx_SET (dest, lxvl));
+ DONE;
})
(define_insn "*lxvl"
@@ -5619,6 +5631,34 @@ (define_insn "lxvll"
"lxvll %x0,%1,%2"
[(set_attr "type" "vecload")])
+;; For lxvrl and lxvrll, use the combiner to eliminate the shift. The
+;; define_expand for lxvl will already incorporate the shift in generating the
+;; insn. The lxvll buitl-in function required the user to have already done
+;; the shift. Defining lxvrll this way, will optimize cases where the user has
+;; done the shift immediately before the built-in.
+(define_insn "*lxvrl"
+ [(set (match_operand:V16QI 0 "vsx_register_operand" "=wa")
+ (unspec:V16QI
+ [(match_operand:DI 1 "gpc_reg_operand" "b")
+ (mem:V16QI (match_dup 1))
+ (ashift:DI (match_operand:DI 2 "register_operand" "r")
+ (const_int 56))]
+ UNSPEC_LXVL))]
+ "TARGET_FUTURE && TARGET_64BIT"
+ "lxvrl %x0,%1,%2"
+ [(set_attr "type" "vecload")])
+
+(define_insn "*lxvrll"
+ [(set (match_operand:V16QI 0 "vsx_register_operand" "=wa")
+ (unspec:V16QI [(match_operand:DI 1 "gpc_reg_operand" "b")
+ (mem:V16QI (match_dup 1))
+ (ashift:DI (match_operand:DI 2 "register_operand" "r")
+ (const_int 56))]
+ UNSPEC_LXVLL))]
+ "TARGET_FUTURE"
+ "lxvrll %x0,%1,%2"
+ [(set_attr "type" "vecload")])
+
;; Expand for builtin xl_len_r
(define_expand "xl_len_r"
[(match_operand:V16QI 0 "vsx_register_operand")
@@ -5650,18 +5690,29 @@ (define_insn "stxvll"
;; Store VSX Vector with Length
(define_expand "stxvl"
- [(set (match_dup 3)
- (ashift:DI (match_operand:DI 2 "register_operand")
- (const_int 56)))
- (set (mem:V16QI (match_operand:DI 1 "gpc_reg_operand"))
- (unspec:V16QI
- [(match_operand:V16QI 0 "vsx_register_operand")
- (mem:V16QI (match_dup 1))
- (match_dup 3)]
- UNSPEC_STXVL))]
+ [(use (match_operand:V16QI 0 "vsx_register_operand"))
+ (use (match_operand:DI 1 "gpc_reg_operand"))
+ (use (match_operand:DI 2 "gpc_reg_operand"))]
"TARGET_P9_VECTOR && TARGET_64BIT"
{
- operands[3] = gen_reg_rtx (DImode);
+ rtx shift_len = gen_rtx_ASHIFT (DImode, operands[2], GEN_INT (56));
+ rtx len;
+
+ if (TARGET_FUTURE)
+ len = shift_len;
+ else
+ {
+ len = gen_reg_rtx (DImode);
+ emit_insn (gen_rtx_SET (len, shift_len));
+ }
+
+ rtx src = operands[0];
+ rtx addr = operands[1];
+ rtx mem = gen_rtx_MEM (V16QImode, addr);
+ rtvec rv = gen_rtvec (3, src, mem, len);
+ rtx stxvl = gen_rtx_UNSPEC (V16QImode, rv, UNSPEC_STXVL);
+ emit_insn (gen_rtx_SET (mem, stxvl));
+ DONE;
})
;; Define optab for vector access with length vectorization exploitation.
@@ -5705,6 +5756,35 @@ (define_insn "*stxvl"
"stxvl %x0,%1,%2"
[(set_attr "type" "vecstore")])
+;; For stxvrl and stxvrll, use the combiner to eliminate the shift. The
+;; define_expand for stxvl will already incorporate the shift in generating the
+;; insn. The stxvll buitl-in function required the user to have already done
+;; the shift. Defining stxvrll this way, will optimize cases where the user
+;; has done the shift immediately before the built-in.
+
+(define_insn "*stxvrl"
+ [(set (mem:V16QI (match_operand:DI 1 "gpc_reg_operand" "b"))
+ (unspec:V16QI
+ [(match_operand:V16QI 0 "vsx_register_operand" "wa")
+ (mem:V16QI (match_dup 1))
+ (ashift:DI (match_operand:DI 2 "register_operand" "r")
+ (const_int 56))]
+ UNSPEC_STXVL))]
+ "TARGET_FUTURE && TARGET_64BIT"
+ "stxvrl %x0,%1,%2"
+ [(set_attr "type" "vecstore")])
+
+(define_insn "*stxvrll"
+ [(set (mem:V16QI (match_operand:DI 1 "gpc_reg_operand" "b"))
+ (unspec:V16QI [(match_operand:V16QI 0 "vsx_register_operand" "wa")
+ (mem:V16QI (match_dup 1))
+ (ashift:DI (match_operand:DI 2 "register_operand" "r")
+ (const_int 56))]
+ UNSPEC_STXVLL))]
+ "TARGET_FUTURE"
+ "stxvrll %x0,%1,%2"
+ [(set_attr "type" "vecstore")])
+
;; Expand for builtin xst_len_r
(define_expand "xst_len_r"
[(match_operand:V16QI 0 "vsx_register_operand" "=wa")
new file mode 100644
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_future_ok } */
+/* { dg-options "-mdejagnu-cpu=future -O2" } */
+
+/* Test whether the lxvrl and stxvrl instructions are generated for
+ -mcpu=future on memory copy operations. */
+
+#ifndef VSIZE
+#define VSIZE 2
+#endif
+
+#ifndef LSIZE
+#define LSIZE 5
+#endif
+
+struct foo {
+ vector unsigned char vc[VSIZE];
+ unsigned char leftover[LSIZE];
+};
+
+void memcpy_ptr (struct foo *p, struct foo *q)
+{
+ __builtin_memcpy ((void *) p, /* lxvrl and stxvrl. */
+ (void *) q,
+ (sizeof (vector unsigned char) * VSIZE) + LSIZE);
+}
+
+/* { dg-final { scan-assembler {\mlxvrl\M} } } */
+/* { dg-final { scan-assembler {\mstxvrl\M} } } */
+/* { dg-final { scan-assembler-not {\mlxvl\M} } } */
+/* { dg-final { scan-assembler-not {\mstxvl\M} } } */