--- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -4237,19 +4237,34 @@ (define_insn "*aarch64_get_lane_extend" [(set_attr "type" "neon_to_gp")] ) -(define_insn "*aarch64_get_lane_zero_extend" +(define_insn "*aarch64_get_lane_extenddi" + [(set (match_operand:DI 0 "register_operand" "=r") + (sign_extend:DI + (vec_select: + (match_operand:VS 1 "register_operand" "w") + (parallel [(match_operand:SI 2 "immediate_operand" "i")]))))] + "TARGET_SIMD" + { + operands[2] = aarch64_endian_lane_rtx (mode, + INTVAL (operands[2])); + return "smov\\t%x0, %1.[%2]"; + } + [(set_attr "type" "neon_to_gp")] +) + +(define_insn "*aarch64_get_lane_zero_extend" [(set (match_operand:GPI 0 "register_operand" "=r") (zero_extend:GPI - (vec_select: - (match_operand:VDQQH 1 "register_operand" "w") + (vec_select: + (match_operand:VDQV_L 1 "register_operand" "w") (parallel [(match_operand:SI 2 "immediate_operand" "i")]))))] "TARGET_SIMD" { - operands[2] = aarch64_endian_lane_rtx (mode, + operands[2] = aarch64_endian_lane_rtx (mode, INTVAL (operands[2])); - return "umov\\t%w0, %1.[%2]"; + return "umov\\t%w0, %1.[%2]"; } - [(set_attr "type" "neon_to_gp")] + [(set_attr "type" "neon_to_gp")] ) ;; Lane extraction of a value, neither sign nor zero extension diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 3ea16dbc2557c6a4f37104d44a49f77f768eb53d..09ae1118371f82ca63146fceb953eb9e820d05a4 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -1911,22 +1911,6 @@ (define_insn "storewb_pair_" ;; Sign/Zero extension ;; ------------------------------------------------------------------- -(define_expand "sidi2" - [(set (match_operand:DI 0 "register_operand") - (ANY_EXTEND:DI (match_operand:SI 1 "nonimmediate_operand")))] - "" -) - -(define_insn "*extendsidi2_aarch64" - [(set (match_operand:DI 0 "register_operand" "=r,r") - (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m")))] - "" - "@ - sxtw\t%0, %w1 - ldrsw\t%0, %1" - [(set_attr "type" "extend,load_4")] -) - (define_insn "*load_pair_extendsidi2_aarch64" [(set (match_operand:DI 0 "register_operand" "=r") (sign_extend:DI (match_operand:SI 1 "aarch64_mem_pair_operand" "Ump"))) @@ -1940,21 +1924,6 @@ (define_insn "*load_pair_extendsidi2_aarch64" [(set_attr "type" "load_8")] ) -(define_insn "*zero_extendsidi2_aarch64" - [(set (match_operand:DI 0 "register_operand" "=r,r,w,w,r,w") - (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m,r,m,w,w")))] - "" - "@ - uxtw\t%0, %w1 - ldr\t%w0, %1 - fmov\t%s0, %w1 - ldr\t%s0, %1 - fmov\t%w0, %s1 - fmov\t%s0, %s1" - [(set_attr "type" "mov_reg,load_4,f_mcr,f_loads,f_mrc,fmov") - (set_attr "arch" "*,*,fp,fp,fp,fp")] -) - (define_insn "*load_pair_zero_extendsidi2_aarch64" [(set (match_operand:DI 0 "register_operand" "=r,w") (zero_extend:DI (match_operand:SI 1 "aarch64_mem_pair_operand" "Ump,Ump"))) @@ -1971,61 +1940,64 @@ (define_insn "*load_pair_zero_extendsidi2_aarch64" (set_attr "arch" "*,fp")] ) -(define_expand "2" - [(set (match_operand:GPI 0 "register_operand") - (ANY_EXTEND:GPI (match_operand:SHORT 1 "nonimmediate_operand")))] - "" -) - -(define_insn "*extend2_aarch64" - [(set (match_operand:GPI 0 "register_operand" "=r,r,r") - (sign_extend:GPI (match_operand:SHORT 1 "nonimmediate_operand" "r,m,w")))] +(define_insn "extend2" + [(set (match_operand:SD_HSDI 0 "register_operand" "=r,r,r") + (sign_extend:SD_HSDI + (match_operand:ALLX 1 "nonimmediate_operand" "r,m,w")))] "" "@ - sxt\t%0, %w1 - ldrs\t%0, %1 - smov\t%0, %1.[0]" + sxt\t%0, %w1 + ldrs\t%0, %1 + smov\t%0, %1.[0]" [(set_attr "type" "extend,load_4,neon_to_gp") (set_attr "arch" "*,*,fp")] ) -(define_insn "*zero_extend2_aarch64" - [(set (match_operand:GPI 0 "register_operand" "=r,r,w,r") - (zero_extend:GPI (match_operand:SHORT 1 "nonimmediate_operand" "r,m,m,w")))] +(define_insn "zero_extend2" + [(set (match_operand:SD_HSDI 0 "register_operand" "=r,r,w,w,r,w") + (zero_extend:SD_HSDI + (match_operand:SI_ONLY 1 "nonimmediate_operand" "r,m,r,m,w,w")))] "" "@ - and\t%0, %1, - ldr\t%w0, %1 - ldr\t%0, %1 - umov\t%w0, %1.[0]" - [(set_attr "type" "logic_imm,load_4,f_loads,neon_to_gp") - (set_attr "arch" "*,*,fp,fp")] -) - -(define_expand "qihi2" - [(set (match_operand:HI 0 "register_operand") - (ANY_EXTEND:HI (match_operand:QI 1 "nonimmediate_operand")))] - "" + uxt\t%0, %w1 + ldr\t%w0, %1 + fmov\t%0, %w1 + ldr\t%0, %1 + fmov\t%w0, %1 + fmov\t%0, %1" + [(set_attr "type" "mov_reg,load_4,f_mcr,f_loads,f_mrc,fmov") + (set_attr "arch" "*,*,fp,fp,fp,fp")] ) -(define_insn "*extendqihi2_aarch64" - [(set (match_operand:HI 0 "register_operand" "=r,r") - (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "r,m")))] +(define_insn "zero_extend2" + [(set (match_operand:SD_HSDI 0 "register_operand" "=r,r,w,w,r,w") + (zero_extend:SD_HSDI + (match_operand:HI_ONLY 1 "nonimmediate_operand" "r,m,r,m,w,w")))] "" "@ - sxtb\t%w0, %w1 - ldrsb\t%w0, %1" - [(set_attr "type" "extend,load_4")] + uxt\t%0, %w1 + ldr\t%w0, %1 + fmov\t%0, %w1 + ldr\t%0, %1 + umov\t%w0, %1.[0] + fmov\t%0, %1" + [(set_attr "type" "mov_reg,load_4,f_mcr,f_loads,f_mrc,fmov") + (set_attr "arch" "*,*,fp16,fp,fp,fp16")] ) -(define_insn "*zero_extendqihi2_aarch64" - [(set (match_operand:HI 0 "register_operand" "=r,r") - (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "r,m")))] +(define_insn "zero_extend2" + [(set (match_operand:SD_HSDI 0 "register_operand" "=r,r,w,r,w") + (zero_extend:SD_HSDI + (match_operand:QI_ONLY 1 "nonimmediate_operand" "r,m,m,w,w")))] "" "@ - and\t%w0, %w1, 255 - ldrb\t%w0, %1" - [(set_attr "type" "logic_imm,load_4")] + uxt\t%0, %w1 + ldr\t%w0, %1 + ldr\t%0, %1 + umov\t%w0, %1.[0] + dup\t%0, %1.[0]" + [(set_attr "type" "mov_reg,load_4,f_loads,f_mrc,fmov") + (set_attr "arch" "*,*,fp,fp,fp")] ) ;; ------------------------------------------------------------------- @@ -5029,15 +5001,15 @@ (define_insn "*and_compare0" [(set_attr "type" "alus_imm")] ) -(define_insn "*ands_compare0" +(define_insn "*ands_compare0" [(set (reg:CC_NZ CC_REGNUM) (compare:CC_NZ - (zero_extend:GPI (match_operand:SHORT 1 "register_operand" "r")) + (zero_extend:SD_HSDI (match_operand:ALLX 1 "register_operand" "r")) (const_int 0))) - (set (match_operand:GPI 0 "register_operand" "=r") - (zero_extend:GPI (match_dup 1)))] + (set (match_operand:SD_HSDI 0 "register_operand" "=r") + (zero_extend:SD_HSDI (match_dup 1)))] "" - "ands\\t%0, %1, " + "ands\\t%0, %1, " [(set_attr "type" "alus_imm")] ) diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 1df09f7fe2eb35aed96113476541e0faa5393551..e904407b2169e589b7007ff966b2d9347a6d0fd2 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -41,6 +41,8 @@ (define_mode_iterator SHORT [QI HI]) ;; Iterators for single modes, for "@" patterns. (define_mode_iterator SI_ONLY [SI]) (define_mode_iterator DI_ONLY [DI]) +(define_mode_iterator HI_ONLY [HI]) +(define_mode_iterator QI_ONLY [QI]) ;; Iterator for all integer modes (up to 64-bit) (define_mode_iterator ALLI [QI HI SI DI]) @@ -1033,7 +1035,7 @@ (define_mode_attr w2 [(HF "x") (SF "x") (DF "w")]) ;; For width of fp registers in fcvt instruction (define_mode_attr fpw [(DI "s") (SI "d")]) -(define_mode_attr short_mask [(HI "65535") (QI "255")]) +(define_mode_attr short_mask [(SI "0xffffffff") (HI "0xffff") (QI "0xff")]) ;; For constraints used in scalar immediate vector moves (define_mode_attr hq [(HI "h") (QI "q")]) diff --git a/gcc/testsuite/gcc.target/aarch64/ands_3.c b/gcc/testsuite/gcc.target/aarch64/ands_3.c index 42cb7f0f0bc86a4aceb09851c31eb2e888d93403..421aa5cea7a51ad810cc9c5653a149cb21bb871c 100644 --- a/gcc/testsuite/gcc.target/aarch64/ands_3.c +++ b/gcc/testsuite/gcc.target/aarch64/ands_3.c @@ -9,4 +9,4 @@ f9 (unsigned char x, int y) return x; } -/* { dg-final { scan-assembler "ands\t(x|w)\[0-9\]+,\[ \t\]*(x|w)\[0-9\]+,\[ \t\]*255" } } */ +/* { dg-final { scan-assembler "ands\t(x|w)\[0-9\]+,\[ \t\]*(x|w)\[0-9\]+,\[ \t\]*0xff" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/slp_1.c b/gcc/testsuite/gcc.target/aarch64/sve/slp_1.c index 8e35e0b574d49913b43c7d8d4f4ba75f127f42e9..03288976b3397cdbe0e822f94f2a6448d9fa9a52 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/slp_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/slp_1.c @@ -51,7 +51,6 @@ TEST_ALL (VEC_PERM) /* { dg-final { scan-assembler-times {\twhilelo\tp[0-7]\.s} 6 } } */ /* { dg-final { scan-assembler-times {\twhilelo\tp[0-7]\.d} 6 } } */ /* { dg-final { scan-assembler-not {\tldr} } } */ -/* { dg-final { scan-assembler-times {\tstr} 2 } } */ -/* { dg-final { scan-assembler-times {\tstr\th[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {\tins\tv[0-9]+\.h\[1\], v[0-9]+\.h\[0\]} 1 } } */ /* { dg-final { scan-assembler-not {\tuqdec} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/tst_5.c b/gcc/testsuite/gcc.target/aarch64/tst_5.c index 0de40a6c47a7d63c1b7a81aeba438a096c0041b8..19034cd74ed07ea4d670c25d9ab3d1cff805a483 100644 --- a/gcc/testsuite/gcc.target/aarch64/tst_5.c +++ b/gcc/testsuite/gcc.target/aarch64/tst_5.c @@ -4,7 +4,7 @@ int f255 (int x) { - if (x & 255) + if (x & 0xff) return 1; return x; } @@ -12,10 +12,10 @@ f255 (int x) int f65535 (int x) { - if (x & 65535) + if (x & 0xffff) return 1; return x; } -/* { dg-final { scan-assembler "tst\t(x|w)\[0-9\]+,\[ \t\]*255" } } */ -/* { dg-final { scan-assembler "tst\t(x|w)\[0-9\]+,\[ \t\]*65535" } } */ +/* { dg-final { scan-assembler "tst\t(x|w)\[0-9\]+,\[ \t\]*0xff" } } */ +/* { dg-final { scan-assembler "tst\t(x|w)\[0-9\]+,\[ \t\]*0xffff" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/tst_6.c b/gcc/testsuite/gcc.target/aarch64/tst_6.c index f15ec114c391fed79cc43b7740fde83fb3d4ea53..1c047cfae214b60e5bf003e6781a277202fcc588 100644 --- a/gcc/testsuite/gcc.target/aarch64/tst_6.c +++ b/gcc/testsuite/gcc.target/aarch64/tst_6.c @@ -7,4 +7,4 @@ foo (long x) return ((short) x != 0) ? x : 1; } -/* { dg-final { scan-assembler "tst\t(x|w)\[0-9\]+,\[ \t\]*65535" } } */ +/* { dg-final { scan-assembler "tst\t(x|w)\[0-9\]+,\[ \t\]*0xffff" } } */