From patchwork Mon Oct 31 11:58:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tamar Christina X-Patchwork-Id: 59651 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id AE6B73853806 for ; Mon, 31 Oct 2022 12:00:46 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org AE6B73853806 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1667217646; bh=GbuvD6we8C52P7Xvv2yIJLB8MjygodYPPTGJolOa/Hw=; h=Date:To:Subject:In-Reply-To:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:Cc:From; b=KR/Q7X8vQYykYZup/DOWq8J4LyzUWu8VhVuFliSJEKTrllOoF+Fm7HDlDyng1NeOV PJXRIJdac0ODOsO+cTZeO1l5JJz+pgLOtUqsxbPhDVNn7GtoSak/r3kkkIrJVKzroq KeeUBUh2qRa8MNE+avFmsMDF7YQAG8yDeBy9/7tM= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from EUR01-DB5-obe.outbound.protection.outlook.com (mail-eopbgr150088.outbound.protection.outlook.com [40.107.15.88]) by sourceware.org (Postfix) with ESMTPS id 6E96B3851C1E for ; Mon, 31 Oct 2022 11:59:05 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 6E96B3851C1E ARC-Seal: i=2; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=pass; b=Uxiw146OAHf0ZFp0k4bMVgfidX4qPAXlwaj4+ZWCYNzOJgBgIoqTE0kud5LdgALkB4a/PuBv490pOSrgb7fKeuV1e/4qpXlXCwTKkrdJQ7zDDGbXJT+W+wB8fpcLtvi88dWihS9ehrxEVNK5r9SAfd+c0hr1vaduEJ33bkisT9QduT4nvV2+jA40S6GaFw/QeI1qxQco/DuYsXQvkslk+7Eu9PYN/iCsmGKXgZpmB++1W4tq1eSBOqXPavePvC6QI7pTvIyYKOqgLZI3+gxQvW3R56NjUkJRG+pEsTejsk7W3UHJrIGPA2f3qj+F4qbS3bkJxME8z8VfL0SP+zXfbA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=GbuvD6we8C52P7Xvv2yIJLB8MjygodYPPTGJolOa/Hw=; b=RufwG+pkB6E8Yd3o5ohsHRm9c777NemS68pyFe19LHh4WUwVFPu6frUZ7lT8vGsJPMh5t5ZHQW/W1T+GhlGLBIKEyZIw45MKGRm1IjNDAHWMFOYhPHJrwC2aezp38Nn3Fome0+zi2YM6EF5RS+5YztAzgIbbWJkkPvbfTO3cNZNV18IT9ZWMQSrIp0JzrZIsvgnmjib5Vg8PaYA9UG7Lp8H92VghAdcYtknhPOh3LDxU53njmc4Qw5pQ8csMk3eZYgJd2aVsh4LhJ++kGvap8F9sL5z9lNAIyvKxytNXFWusUt96j70ZO4HBDoyfmyVAOptLMYRzop3m0DWulaQ44w== ARC-Authentication-Results: i=2; mx.microsoft.com 1; spf=pass (sender ip is 63.35.35.123) smtp.rcpttodomain=gcc.gnu.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com; arc=pass (0 oda=1 ltdi=1 spf=[1,1,smtp.mailfrom=arm.com] dkim=[1,1,header.d=arm.com] dmarc=[1,1,header.from=arm.com]) Received: from DB9PR02CA0028.eurprd02.prod.outlook.com (2603:10a6:10:1d9::33) by PA4PR08MB7385.eurprd08.prod.outlook.com (2603:10a6:102:2a0::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5769.15; Mon, 31 Oct 2022 11:59:02 +0000 Received: from DBAEUR03FT023.eop-EUR03.prod.protection.outlook.com (2603:10a6:10:1d9:cafe::a) by DB9PR02CA0028.outlook.office365.com (2603:10a6:10:1d9::33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5769.15 via Frontend Transport; Mon, 31 Oct 2022 11:59:02 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; pr=C Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by DBAEUR03FT023.mail.protection.outlook.com (100.127.142.253) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5769.14 via Frontend Transport; Mon, 31 Oct 2022 11:59:02 +0000 Received: ("Tessian outbound 58faf9791229:v130"); Mon, 31 Oct 2022 11:59:02 +0000 X-CheckRecipientChecked: true X-CR-MTA-CID: b0559d7bca7c3507 X-CR-MTA-TID: 64aa7808 Received: from c1694a330e7c.2 by 64aa7808-outbound-1.mta.getcheckrecipient.com id C4D91AC3-947B-427E-B065-375B4160E6A9.1; Mon, 31 Oct 2022 11:58:55 +0000 Received: from EUR04-HE1-obe.outbound.protection.outlook.com by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id c1694a330e7c.2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Mon, 31 Oct 2022 11:58:55 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=ahZbY2ODi7NNQEyld05kSM8tyei0ijttGQvF31BNCLgNBb3dnqhrZ3RuId5k7AeRjG0W1WvwZVFsVQA17CqDbrBqBeChWfKIznyHwEKN5yQnSaB858aG7guE0moKTso7YRj2d/nOEuK1LhE/60zXju3cWut5OqolSVpCpsrEZCfM93lPpnSgUmY8Sv0yOCdcHWsr3RZ30QcEBRUKYrp0ufW7+whKFBimBPRWbhi9PotHiXGgWmlm++lpo/PRTP89OqJxcGBiMxAfHhlsjSe9M+/yrF7VFkkZ4nLP6OsFpn6c6q+UG6SrH1AEEDaio43g3B7lLwA7McSeBOFCBHl4Bw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=GbuvD6we8C52P7Xvv2yIJLB8MjygodYPPTGJolOa/Hw=; b=eR4xOrcBbgfLF32W+I69LEiOli4c5nF7kqR1Jbw7jTq2cJ9s36LlLLDTw1AnN/CW3oOKvabYW9cPeoNYPVzLm6t6Z9i5J25f6Fd6M1RI4LHJbqIcXYBamx0wkm9OWGT5vJz843Oj7ejZ5o7mecUrYZBTQ+2pppIuSDv4LWumAXSeNh9kDNJkZXGv1rYarAJF85hKrN89NB9aPO3WujsTPcfMwf0pjFWBpnpPrsmxgZdp4vm9BPqdw1qmjIFvot+VU24K5laoSN9dkmCvg6aKhgP3r3Vnh95x6t2Qt+ptfVSJ4707uZqRH7K8013t40oSjcO5HEwdB4MdveKDxydgRw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none Authentication-Results-Original: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; Received: from VI1PR08MB5325.eurprd08.prod.outlook.com (2603:10a6:803:13e::17) by AS2PR08MB8717.eurprd08.prod.outlook.com (2603:10a6:20b:55d::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5769.14; Mon, 31 Oct 2022 11:58:53 +0000 Received: from VI1PR08MB5325.eurprd08.prod.outlook.com ([fe80::c57d:50c2:3502:a52]) by VI1PR08MB5325.eurprd08.prod.outlook.com ([fe80::c57d:50c2:3502:a52%4]) with mapi id 15.20.5769.019; Mon, 31 Oct 2022 11:58:53 +0000 Date: Mon, 31 Oct 2022 11:58:50 +0000 To: gcc-patches@gcc.gnu.org Subject: [PATCH 5/8]AArch64 aarch64: Make existing V2HF be usable. Message-ID: Content-Disposition: inline In-Reply-To: X-ClientProxiedBy: LO4P123CA0489.GBRP123.PROD.OUTLOOK.COM (2603:10a6:600:1ab::8) To VI1PR08MB5325.eurprd08.prod.outlook.com (2603:10a6:803:13e::17) MIME-Version: 1.0 X-MS-TrafficTypeDiagnostic: VI1PR08MB5325:EE_|AS2PR08MB8717:EE_|DBAEUR03FT023:EE_|PA4PR08MB7385:EE_ X-MS-Office365-Filtering-Correlation-Id: 73d59646-5faa-4bc8-2867-08dabb374d90 x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: gPgn4EpSlKRuG+Em7xxvjqpDQ7gDGplOxqy3tGFed9MQSOFL9aZkbwWz4d+9j+EdWhhUJ3BZm8puHbIUORi6VYheHCBkB0acGQdWhznJCeX/ltthor2Jl3IA6dn3Gd3K/OpJkBDp8VYFFtmnTizQU+2Wi5RDolPZnxp8JeBXG/k/RD2AL6r/rm4BE+3Z8IiSjj2SOXJpXRcYQPtcPD390Ksru42ZrYXCvJivpj1VdmGSCARvkGCmuJfyUHc1qzEpt3APuMLYTbdeB0RomZoiVASUr2A/a32dMpu/Rl21WiNSCBW9h+JfCDRMnc4tRoYiNEdhyfejIsjAOPmzDDJZpsP90RcX5IPyH0aDP9V8BszW0nFzwzzjaTVyjDz/BAgcGw4y0oQHaleYiFr0zZw7UPLt+9arrtuNb1lZEy2/5t77YNjq9eGyC4TzpMiMjJWdErvBs5VfZo9RJQUprh4a74R/Iqq6DHqYT/BuN0WcMhw8EEcUGauXcf7g0YWJLwa1xwhVOH/IR24d6LjDfv0KMEkeLq/PapwKON4E/U/g1ZRoz4/Aj0QsouYtIWST31frtxAOROyyP2VV2qktj0eV8M3aQcNnWJI26jNKaIv5GKPgAlhnvtNz9R8ckB7ZfEV9DGbDXL703ZLP3VJp4NGRMZgcJCXB41hxGUkQ7MoV5MyiypxY0f+jMeD00cnFOan+it/SGoOJdRbyL4pQUIi9svPo9IbUdGVPFWixXI1LigNaqeEr4pTdljbTRxl74BmbcUD5TKEAttHqykVxnTVcOPFG8tUFrWL0SDOGb6CajyRrt9IcG39k8bhzeoAu98j1aO3af75kg+WMflqzYVk59zlNCoMeOjKWOoj5sB5Bm+4= X-Forefront-Antispam-Report-Untrusted: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:VI1PR08MB5325.eurprd08.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230022)(4636009)(346002)(376002)(39860400002)(136003)(396003)(366004)(451199015)(478600001)(8676002)(38100700002)(84970400001)(6486002)(316002)(86362001)(6512007)(26005)(4743002)(66476007)(4326008)(41300700001)(186003)(83380400001)(235185007)(2906002)(33964004)(66946007)(2616005)(8936002)(30864003)(6916009)(66556008)(36756003)(5660300002)(44832011)(44144004)(6506007)(67856001)(2700100001); DIR:OUT; SFP:1101; X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS2PR08MB8717 Original-Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; X-EOPAttributedMessage: 0 X-MS-Exchange-Transport-CrossTenantHeadersStripped: DBAEUR03FT023.eop-EUR03.prod.protection.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: e9b592e1-fc7a-4b6a-1cca-08dabb3747bc X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: yS9pZjM7O72lD66W8R85RvOUmHNAkCYY2ta8L6rOdeR5zdUoLJ5WHfO8ltCudKrpEd31QjuC+RmTnzx2J5YerhAZ6lcOwVx3CHlC01MusWbZhc9skB0dgp9PDlaNxu2OpXTBc1l0PvkN5VhtgRPUQlpHwKe/CYP8p6oreS4Eqj0j9CnHB8aauiCJM33wM5eh9/3HAEwbo3qGNIAQdoAfjt7s6RU/aahDYMF03jCBx1JXjCYcr/hAUq5BnLbnHcEGzmX9blPKjavIp871gIpjTB5QyxHYfouhloeUgACdtYpeVVr7WxErJKsmubuEbPXG93/refFewi6kq+t7WPH3EMQZka1jN7CT2j0zqdAq48IXECDWPOvJrzcdmZSivRiZgzfv/0i4wCCXXc6p45PQSupG1oCTRA94Era17bYdKI3KoogfEchAlfWyQrYOcdOggWm3KEHIhxRsYHjoGVr1tEIIzfzDMzfZVPt3+Iev292BEI2UsIpmxxQ+lShzQIyUDOEVTtuqXV3i/gM72qjzbZxUSjV9F+/hYZFOXR4gvnydX9WXcrJ7u2EuUoilxouvidZcKbBP4R9DG//nNVtacveuKnYGKTqzc78wo0AEe6V37VVRGN1/U5B0FHaggSG8i6iQik6UWdddQbPvWIZ41Lv3ziL/QuNW/eRbWzoIOkBVg+wkEnppN18yW72/sfiwkzbsCgJEsRa9GKJPO4vQ3Zm8PAL67scFf/7DlNS/Su6Gynx4ZIpX0Vy9X+nLhM8gXLIZF6YPbqoyCnaXoviU9+nVpvO52rbKssv12PpqAw7xlO69RYeFdU0CY/e7ByX1yPBiqdvqKlvAAPSExR9JyqqmTa/sMb10/AWUep8mveWdKLTgKzqsp27TXdtUDniMgTthZ5K9CDU7nr6d2q/q6A== X-Forefront-Antispam-Report: CIP:63.35.35.123; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(13230022)(4636009)(396003)(39860400002)(376002)(136003)(346002)(451199015)(46966006)(40470700004)(36840700001)(47076005)(81166007)(36860700001)(40460700003)(356005)(82740400003)(86362001)(44832011)(2906002)(30864003)(5660300002)(235185007)(8676002)(6512007)(41300700001)(70206006)(2616005)(4326008)(82310400005)(6506007)(70586007)(33964004)(6486002)(186003)(336012)(478600001)(4743002)(8936002)(316002)(6916009)(44144004)(26005)(40480700001)(84970400001)(83380400001)(36756003)(2700100001)(67856001); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Oct 2022 11:59:02.5078 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 73d59646-5faa-4bc8-2867-08dabb374d90 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DBAEUR03FT023.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA4PR08MB7385 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, KAM_LOTSOFHASH, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SCC_10_SHORT_WORD_LINES, SCC_5_SHORT_WORD_LINES, SPF_HELO_PASS, SPF_NONE, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tamar Christina via Gcc-patches From: Tamar Christina Reply-To: Tamar Christina Cc: Richard.Earnshaw@arm.com, nd@arm.com, richard.sandiford@arm.com, Marcus.Shawcroft@arm.com Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Hi All, The backend has an existing V2HFmode that is used by pairwise operations. This mode was however never made fully functional. Amongst other things it was never declared as a vector type which made it unusable from the mid-end. It's also lacking an implementation for load/stores so reload ICEs if this mode is every used. This finishes the implementation by providing the above. Note that I have created a new iterator VHSDF_P instead of extending VHSDF because the previous iterator is used in far more things than just load/stores. It's also used for instance in intrinsics and extending this would force me to provide support for mangling the type while we never expose it through intrinsics. Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. Ok for master? Thanks, Tamar gcc/ChangeLog: * config/aarch64/aarch64-simd.md (*aarch64_simd_movv2hf): New. (mov, movmisalign, aarch64_dup_lane, aarch64_store_lane0, aarch64_simd_vec_set, @aarch64_simd_vec_copy_lane, vec_set, reduc__scal_, reduc__scal_, aarch64_reduc__internal, aarch64_get_lane, vec_init, vec_extract): Support V2HF. * config/aarch64/aarch64.cc (aarch64_classify_vector_mode): Add E_V2HFmode. * config/aarch64/iterators.md (VHSDF_P): New. (V2F, VALL_F16_FULL, nunits, Vtype, Vmtype, Vetype, stype, VEL, Vel, q, vp): Add V2HF. * config/arm/types.md (neon_fp_reduc_add_h): New. gcc/testsuite/ChangeLog: * gcc.target/aarch64/sve/slp_1.c: Update testcase. --- inline copy of patch -- diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 25aed74f8cf939562ed65a578fe32ca76605b58a..93a2888f567460ad10ec050ea7d4f701df4729d1 100644 --- diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 25aed74f8cf939562ed65a578fe32ca76605b58a..93a2888f567460ad10ec050ea7d4f701df4729d1 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -19,10 +19,10 @@ ;; . (define_expand "mov" - [(set (match_operand:VALL_F16 0 "nonimmediate_operand") - (match_operand:VALL_F16 1 "general_operand"))] + [(set (match_operand:VALL_F16_FULL 0 "nonimmediate_operand") + (match_operand:VALL_F16_FULL 1 "general_operand"))] "TARGET_SIMD" - " +{ /* Force the operand into a register if it is not an immediate whose use can be replaced with xzr. If the mode is 16 bytes wide, then we will be doing @@ -46,12 +46,11 @@ (define_expand "mov" aarch64_expand_vector_init (operands[0], operands[1]); DONE; } - " -) +}) (define_expand "movmisalign" - [(set (match_operand:VALL_F16 0 "nonimmediate_operand") - (match_operand:VALL_F16 1 "general_operand"))] + [(set (match_operand:VALL_F16_FULL 0 "nonimmediate_operand") + (match_operand:VALL_F16_FULL 1 "general_operand"))] "TARGET_SIMD && !STRICT_ALIGNMENT" { /* This pattern is not permitted to fail during expansion: if both arguments @@ -85,10 +84,10 @@ (define_insn "aarch64_simd_dup" ) (define_insn "aarch64_dup_lane" - [(set (match_operand:VALL_F16 0 "register_operand" "=w") - (vec_duplicate:VALL_F16 + [(set (match_operand:VALL_F16_FULL 0 "register_operand" "=w") + (vec_duplicate:VALL_F16_FULL (vec_select: - (match_operand:VALL_F16 1 "register_operand" "w") + (match_operand:VALL_F16_FULL 1 "register_operand" "w") (parallel [(match_operand:SI 2 "immediate_operand" "i")]) )))] "TARGET_SIMD" @@ -142,6 +141,29 @@ (define_insn "*aarch64_simd_mov" mov_reg, neon_move")] ) +(define_insn "*aarch64_simd_movv2hf" + [(set (match_operand:V2HF 0 "nonimmediate_operand" + "=w, m, m, w, ?r, ?w, ?r, w, w") + (match_operand:V2HF 1 "general_operand" + "m, Dz, w, w, w, r, r, Dz, Dn"))] + "TARGET_SIMD_F16INST + && (register_operand (operands[0], V2HFmode) + || aarch64_simd_reg_or_zero (operands[1], V2HFmode))" + "@ + ldr\\t%s0, %1 + str\\twzr, %0 + str\\t%s1, %0 + mov\\t%0.2s[0], %1.2s[0] + umov\\t%w0, %1.s[0] + fmov\\t%s0, %1 + mov\\t%0, %1 + movi\\t%d0, 0 + * return aarch64_output_simd_mov_immediate (operands[1], 32);" + [(set_attr "type" "neon_load1_1reg, store_8, neon_store1_1reg,\ + neon_logic, neon_to_gp, f_mcr,\ + mov_reg, neon_move, neon_move")] +) + (define_insn "*aarch64_simd_mov" [(set (match_operand:VQMOV 0 "nonimmediate_operand" "=w, Umn, m, w, ?r, ?w, ?r, w") @@ -182,7 +204,7 @@ (define_insn "*aarch64_simd_mov" (define_insn "aarch64_store_lane0" [(set (match_operand: 0 "memory_operand" "=m") - (vec_select: (match_operand:VALL_F16 1 "register_operand" "w") + (vec_select: (match_operand:VALL_F16_FULL 1 "register_operand" "w") (parallel [(match_operand 2 "const_int_operand" "n")])))] "TARGET_SIMD && ENDIAN_LANE_N (, INTVAL (operands[2])) == 0" @@ -1035,11 +1057,11 @@ (define_insn "one_cmpl2" ) (define_insn "aarch64_simd_vec_set" - [(set (match_operand:VALL_F16 0 "register_operand" "=w,w,w") - (vec_merge:VALL_F16 - (vec_duplicate:VALL_F16 + [(set (match_operand:VALL_F16_FULL 0 "register_operand" "=w,w,w") + (vec_merge:VALL_F16_FULL + (vec_duplicate:VALL_F16_FULL (match_operand: 1 "aarch64_simd_nonimmediate_operand" "w,?r,Utv")) - (match_operand:VALL_F16 3 "register_operand" "0,0,0") + (match_operand:VALL_F16_FULL 3 "register_operand" "0,0,0") (match_operand:SI 2 "immediate_operand" "i,i,i")))] "TARGET_SIMD" { @@ -1061,14 +1083,14 @@ (define_insn "aarch64_simd_vec_set" ) (define_insn "@aarch64_simd_vec_copy_lane" - [(set (match_operand:VALL_F16 0 "register_operand" "=w") - (vec_merge:VALL_F16 - (vec_duplicate:VALL_F16 + [(set (match_operand:VALL_F16_FULL 0 "register_operand" "=w") + (vec_merge:VALL_F16_FULL + (vec_duplicate:VALL_F16_FULL (vec_select: - (match_operand:VALL_F16 3 "register_operand" "w") + (match_operand:VALL_F16_FULL 3 "register_operand" "w") (parallel [(match_operand:SI 4 "immediate_operand" "i")]))) - (match_operand:VALL_F16 1 "register_operand" "0") + (match_operand:VALL_F16_FULL 1 "register_operand" "0") (match_operand:SI 2 "immediate_operand" "i")))] "TARGET_SIMD" { @@ -1376,7 +1398,7 @@ (define_insn "vec_shr_" ) (define_expand "vec_set" - [(match_operand:VALL_F16 0 "register_operand") + [(match_operand:VALL_F16_FULL 0 "register_operand") (match_operand: 1 "aarch64_simd_nonimmediate_operand") (match_operand:SI 2 "immediate_operand")] "TARGET_SIMD" @@ -3503,7 +3525,7 @@ (define_insn "popcount2" ;; gimple_fold'd to the IFN_REDUC_(MAX|MIN) function. (This is FP smax/smin). (define_expand "reduc__scal_" [(match_operand: 0 "register_operand") - (unspec: [(match_operand:VHSDF 1 "register_operand")] + (unspec: [(match_operand:VHSDF_P 1 "register_operand")] FMAXMINV)] "TARGET_SIMD" { @@ -3518,7 +3540,7 @@ (define_expand "reduc__scal_" (define_expand "reduc__scal_" [(match_operand: 0 "register_operand") - (unspec: [(match_operand:VHSDF 1 "register_operand")] + (unspec: [(match_operand:VHSDF_P 1 "register_operand")] FMAXMINNMV)] "TARGET_SIMD" { @@ -3562,8 +3584,8 @@ (define_insn "aarch64_reduc__internalv2si" ) (define_insn "aarch64_reduc__internal" - [(set (match_operand:VHSDF 0 "register_operand" "=w") - (unspec:VHSDF [(match_operand:VHSDF 1 "register_operand" "w")] + [(set (match_operand:VHSDF_P 0 "register_operand" "=w") + (unspec:VHSDF_P [(match_operand:VHSDF_P 1 "register_operand" "w")] FMAXMINV))] "TARGET_SIMD" "\\t%0, %1." @@ -4208,7 +4230,7 @@ (define_insn "*aarch64_get_lane_zero_extend" (define_insn_and_split "aarch64_get_lane" [(set (match_operand: 0 "aarch64_simd_nonimmediate_operand" "=?r, w, Utv") (vec_select: - (match_operand:VALL_F16 1 "register_operand" "w, w, w") + (match_operand:VALL_F16_FULL 1 "register_operand" "w, w, w") (parallel [(match_operand:SI 2 "immediate_operand" "i, i, i")])))] "TARGET_SIMD" { @@ -7989,7 +8011,7 @@ (define_expand "aarch64_st1" ;; Standard pattern name vec_init. (define_expand "vec_init" - [(match_operand:VALL_F16 0 "register_operand") + [(match_operand:VALL_F16_FULL 0 "register_operand") (match_operand 1 "" "")] "TARGET_SIMD" { @@ -8068,7 +8090,7 @@ (define_insn "aarch64_urecpe" (define_expand "vec_extract" [(match_operand: 0 "aarch64_simd_nonimmediate_operand") - (match_operand:VALL_F16 1 "register_operand") + (match_operand:VALL_F16_FULL 1 "register_operand") (match_operand:SI 2 "immediate_operand")] "TARGET_SIMD" { diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index f05bac713e88ea8c7feaa2367d55bd523ca66f57..1e08f8453688210afe1566092b19b59c9bdd0c97 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -3566,6 +3566,7 @@ aarch64_classify_vector_mode (machine_mode mode) case E_V8BFmode: case E_V4SFmode: case E_V2DFmode: + case E_V2HFmode: return TARGET_SIMD ? VEC_ADVSIMD : 0; default: diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 37d8161a33b1c399d80be82afa67613a087389d4..1df09f7fe2eb35aed96113476541e0faa5393551 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -160,6 +160,10 @@ (define_mode_iterator VDQF [V2SF V4SF V2DF]) (define_mode_iterator VHSDF [(V4HF "TARGET_SIMD_F16INST") (V8HF "TARGET_SIMD_F16INST") V2SF V4SF V2DF]) +;; Advanced SIMD Float modes suitable for pairwise operations. +(define_mode_iterator VHSDF_P [(V4HF "TARGET_SIMD_F16INST") + (V8HF "TARGET_SIMD_F16INST") + V2SF V4SF V2DF (V2HF "TARGET_SIMD_F16INST")]) ;; Advanced SIMD Float modes, and DF. (define_mode_iterator VDQF_DF [V2SF V4SF V2DF DF]) @@ -188,15 +192,23 @@ (define_mode_iterator VDQF_COND [V2SF V2SI V4SF V4SI V2DF V2DI]) (define_mode_iterator VALLF [V2SF V4SF V2DF SF DF]) ;; Advanced SIMD Float modes with 2 elements. -(define_mode_iterator V2F [V2SF V2DF]) +(define_mode_iterator V2F [V2SF V2DF V2HF]) ;; All Advanced SIMD modes on which we support any arithmetic operations. (define_mode_iterator VALL [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF]) -;; All Advanced SIMD modes suitable for moving, loading, and storing. +;; All Advanced SIMD modes suitable for moving, loading, and storing +;; except V2HF. (define_mode_iterator VALL_F16 [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V4HF V8HF V4BF V8BF V2SF V4SF V2DF]) +;; All Advanced SIMD modes suitable for moving, loading, and storing +;; including V2HF +(define_mode_iterator VALL_F16_FULL [V8QI V16QI V4HI V8HI V2SI V4SI V2DI + V4HF V8HF V4BF V8BF V2SF V4SF V2DF + (V2HF "TARGET_SIMD_F16INST")]) + + ;; The VALL_F16 modes except the 128-bit 2-element ones. (define_mode_iterator VALL_F16_NO_V2Q [V8QI V16QI V4HI V8HI V2SI V4SI V4HF V8HF V2SF V4SF]) @@ -1076,7 +1088,7 @@ (define_mode_attr nunits [(V8QI "8") (V16QI "16") (V2SF "2") (V4SF "4") (V1DF "1") (V2DF "2") (DI "1") (DF "1") - (V8DI "8")]) + (V8DI "8") (V2HF "2")]) ;; Map a mode to the number of bits in it, if the size of the mode ;; is constant. @@ -1090,6 +1102,7 @@ (define_mode_attr s [(HF "h") (SF "s") (DF "d") (SI "s") (DI "d")]) ;; Give the length suffix letter for a sign- or zero-extension. (define_mode_attr size [(QI "b") (HI "h") (SI "w")]) +(define_mode_attr sizel [(QI "b") (HI "h") (SI "")]) ;; Give the number of bits in the mode (define_mode_attr sizen [(QI "8") (HI "16") (SI "32") (DI "64")]) @@ -1134,8 +1147,9 @@ (define_mode_attr Vtype [(V8QI "8b") (V16QI "16b") (V2SI "2s") (V4SI "4s") (DI "1d") (DF "1d") (V2DI "2d") (V2SF "2s") - (V4SF "4s") (V2DF "2d") - (V4HF "4h") (V8HF "8h") + (V2HF "2h") (V4SF "4s") + (V2DF "2d") (V4HF "4h") + (V8HF "8h") (V2x8QI "8b") (V2x4HI "4h") (V2x2SI "2s") (V2x1DI "1d") (V2x4HF "4h") (V2x2SF "2s") @@ -1175,9 +1189,10 @@ (define_mode_attr Vmtype [(V8QI ".8b") (V16QI ".16b") (V4HI ".4h") (V8HI ".8h") (V2SI ".2s") (V4SI ".4s") (V2DI ".2d") (V4HF ".4h") - (V8HF ".8h") (V4BF ".4h") - (V8BF ".8h") (V2SF ".2s") - (V4SF ".4s") (V2DF ".2d") + (V8HF ".8h") (V2HF ".2h") + (V4BF ".4h") (V8BF ".8h") + (V2SF ".2s") (V4SF ".4s") + (V2DF ".2d") (DI "") (SI "") (HI "") (QI "") (TI "") (HF "") @@ -1193,7 +1208,7 @@ (define_mode_attr Vmntype [(V8HI ".8b") (V4SI ".4h") (define_mode_attr Vetype [(V8QI "b") (V16QI "b") (V4HI "h") (V8HI "h") (V2SI "s") (V4SI "s") - (V2DI "d") + (V2DI "d") (V2HF "h") (V4HF "h") (V8HF "h") (V2SF "s") (V4SF "s") (V2DF "d") @@ -1285,7 +1300,7 @@ (define_mode_attr Vcwtype [(VNx16QI "b") (VNx8QI "h") (VNx4QI "w") (VNx2QI "d") ;; more accurately. (define_mode_attr stype [(V8QI "b") (V16QI "b") (V4HI "s") (V8HI "s") (V2SI "s") (V4SI "s") (V2DI "d") (V4HF "s") - (V8HF "s") (V2SF "s") (V4SF "s") (V2DF "d") + (V8HF "s") (V2SF "s") (V4SF "s") (V2DF "d") (V2HF "s") (HF "s") (SF "s") (DF "d") (QI "b") (HI "s") (SI "s") (DI "d")]) @@ -1360,8 +1375,8 @@ (define_mode_attr VEL [(V8QI "QI") (V16QI "QI") (V4HF "HF") (V8HF "HF") (V2SF "SF") (V4SF "SF") (DF "DF") (V2DF "DF") - (SI "SI") (HI "HI") - (QI "QI") + (SI "SI") (V2HF "HF") + (QI "QI") (HI "HI") (V4BF "BF") (V8BF "BF") (VNx16QI "QI") (VNx8QI "QI") (VNx4QI "QI") (VNx2QI "QI") (VNx8HI "HI") (VNx4HI "HI") (VNx2HI "HI") @@ -1381,7 +1396,7 @@ (define_mode_attr Vel [(V8QI "qi") (V16QI "qi") (V2SF "sf") (V4SF "sf") (V2DF "df") (DF "df") (SI "si") (HI "hi") - (QI "qi") + (QI "qi") (V2HF "hf") (V4BF "bf") (V8BF "bf") (VNx16QI "qi") (VNx8QI "qi") (VNx4QI "qi") (VNx2QI "qi") (VNx8HI "hi") (VNx4HI "hi") (VNx2HI "hi") @@ -1866,7 +1881,7 @@ (define_mode_attr q [(V8QI "") (V16QI "_q") (V4HF "") (V8HF "_q") (V4BF "") (V8BF "_q") (V2SF "") (V4SF "_q") - (V2DF "_q") + (V2HF "") (V2DF "_q") (QI "") (HI "") (SI "") (DI "") (HF "") (SF "") (DF "") (V2x8QI "") (V2x16QI "_q") (V2x4HI "") (V2x8HI "_q") @@ -1905,6 +1920,7 @@ (define_mode_attr vp [(V8QI "v") (V16QI "v") (V2SI "p") (V4SI "v") (V2DI "p") (V2DF "p") (V2SF "p") (V4SF "v") + (V2HF "p") (V4HF "v") (V8HF "v")]) (define_mode_attr vsi2qi [(V2SI "v8qi") (V4SI "v16qi") diff --git a/gcc/config/arm/types.md b/gcc/config/arm/types.md index 7d0504bdd944e9c0d1b545b0b66a9a1adc808714..3cfbc7a93cca1bea4925853e51d0a147c5722247 100644 --- a/gcc/config/arm/types.md +++ b/gcc/config/arm/types.md @@ -483,6 +483,7 @@ (define_attr "autodetect_type" ; neon_fp_minmax_s_q ; neon_fp_minmax_d ; neon_fp_minmax_d_q +; neon_fp_reduc_add_h ; neon_fp_reduc_add_s ; neon_fp_reduc_add_s_q ; neon_fp_reduc_add_d @@ -1033,6 +1034,7 @@ (define_attr "type" neon_fp_minmax_d,\ neon_fp_minmax_d_q,\ \ + neon_fp_reduc_add_h,\ neon_fp_reduc_add_s,\ neon_fp_reduc_add_s_q,\ neon_fp_reduc_add_d,\ @@ -1257,8 +1259,8 @@ (define_attr "is_neon_type" "yes,no" neon_fp_compare_d, neon_fp_compare_d_q, neon_fp_minmax_s,\ neon_fp_minmax_s_q, neon_fp_minmax_d, neon_fp_minmax_d_q,\ neon_fp_neg_s, neon_fp_neg_s_q, neon_fp_neg_d, neon_fp_neg_d_q,\ - neon_fp_reduc_add_s, neon_fp_reduc_add_s_q, neon_fp_reduc_add_d,\ - neon_fp_reduc_add_d_q, neon_fp_reduc_minmax_s, + neon_fp_reduc_add_h, neon_fp_reduc_add_s, neon_fp_reduc_add_s_q,\ + neon_fp_reduc_add_d, neon_fp_reduc_add_d_q, neon_fp_reduc_minmax_s,\ neon_fp_reduc_minmax_s_q, neon_fp_reduc_minmax_d,\ neon_fp_reduc_minmax_d_q,\ neon_fp_cvt_narrow_s_q, neon_fp_cvt_narrow_d_q,\ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/slp_1.c b/gcc/testsuite/gcc.target/aarch64/sve/slp_1.c index 07d71a63414b1066ea431e287286ad048515711a..8e35e0b574d49913b43c7d8d4f4ba75f127f42e9 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/slp_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/slp_1.c @@ -30,11 +30,9 @@ vec_slp_##TYPE (TYPE *restrict a, TYPE b, TYPE c, int n) \ TEST_ALL (VEC_PERM) /* We should use one DUP for each of the 8-, 16- and 32-bit types, - although we currently use LD1RW for _Float16. We should use two - DUPs for each of the three 64-bit types. */ + We should use two DUPs for each of the three 64-bit types. */ /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.h, [hw]} 2 } } */ -/* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.s, [sw]} 2 } } */ -/* { dg-final { scan-assembler-times {\tld1rw\tz[0-9]+\.s, } 1 } } */ +/* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.s, [sw]} 3 } } */ /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.d, [dx]} 9 } } */ /* { dg-final { scan-assembler-times {\tzip1\tz[0-9]+\.d, z[0-9]+\.d, z[0-9]+\.d\n} 3 } } */ /* { dg-final { scan-assembler-not {\tzip2\t} } } */ --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -19,10 +19,10 @@ ;; . (define_expand "mov" - [(set (match_operand:VALL_F16 0 "nonimmediate_operand") - (match_operand:VALL_F16 1 "general_operand"))] + [(set (match_operand:VALL_F16_FULL 0 "nonimmediate_operand") + (match_operand:VALL_F16_FULL 1 "general_operand"))] "TARGET_SIMD" - " +{ /* Force the operand into a register if it is not an immediate whose use can be replaced with xzr. If the mode is 16 bytes wide, then we will be doing @@ -46,12 +46,11 @@ (define_expand "mov" aarch64_expand_vector_init (operands[0], operands[1]); DONE; } - " -) +}) (define_expand "movmisalign" - [(set (match_operand:VALL_F16 0 "nonimmediate_operand") - (match_operand:VALL_F16 1 "general_operand"))] + [(set (match_operand:VALL_F16_FULL 0 "nonimmediate_operand") + (match_operand:VALL_F16_FULL 1 "general_operand"))] "TARGET_SIMD && !STRICT_ALIGNMENT" { /* This pattern is not permitted to fail during expansion: if both arguments @@ -85,10 +84,10 @@ (define_insn "aarch64_simd_dup" ) (define_insn "aarch64_dup_lane" - [(set (match_operand:VALL_F16 0 "register_operand" "=w") - (vec_duplicate:VALL_F16 + [(set (match_operand:VALL_F16_FULL 0 "register_operand" "=w") + (vec_duplicate:VALL_F16_FULL (vec_select: - (match_operand:VALL_F16 1 "register_operand" "w") + (match_operand:VALL_F16_FULL 1 "register_operand" "w") (parallel [(match_operand:SI 2 "immediate_operand" "i")]) )))] "TARGET_SIMD" @@ -142,6 +141,29 @@ (define_insn "*aarch64_simd_mov" mov_reg, neon_move")] ) +(define_insn "*aarch64_simd_movv2hf" + [(set (match_operand:V2HF 0 "nonimmediate_operand" + "=w, m, m, w, ?r, ?w, ?r, w, w") + (match_operand:V2HF 1 "general_operand" + "m, Dz, w, w, w, r, r, Dz, Dn"))] + "TARGET_SIMD_F16INST + && (register_operand (operands[0], V2HFmode) + || aarch64_simd_reg_or_zero (operands[1], V2HFmode))" + "@ + ldr\\t%s0, %1 + str\\twzr, %0 + str\\t%s1, %0 + mov\\t%0.2s[0], %1.2s[0] + umov\\t%w0, %1.s[0] + fmov\\t%s0, %1 + mov\\t%0, %1 + movi\\t%d0, 0 + * return aarch64_output_simd_mov_immediate (operands[1], 32);" + [(set_attr "type" "neon_load1_1reg, store_8, neon_store1_1reg,\ + neon_logic, neon_to_gp, f_mcr,\ + mov_reg, neon_move, neon_move")] +) + (define_insn "*aarch64_simd_mov" [(set (match_operand:VQMOV 0 "nonimmediate_operand" "=w, Umn, m, w, ?r, ?w, ?r, w") @@ -182,7 +204,7 @@ (define_insn "*aarch64_simd_mov" (define_insn "aarch64_store_lane0" [(set (match_operand: 0 "memory_operand" "=m") - (vec_select: (match_operand:VALL_F16 1 "register_operand" "w") + (vec_select: (match_operand:VALL_F16_FULL 1 "register_operand" "w") (parallel [(match_operand 2 "const_int_operand" "n")])))] "TARGET_SIMD && ENDIAN_LANE_N (, INTVAL (operands[2])) == 0" @@ -1035,11 +1057,11 @@ (define_insn "one_cmpl2" ) (define_insn "aarch64_simd_vec_set" - [(set (match_operand:VALL_F16 0 "register_operand" "=w,w,w") - (vec_merge:VALL_F16 - (vec_duplicate:VALL_F16 + [(set (match_operand:VALL_F16_FULL 0 "register_operand" "=w,w,w") + (vec_merge:VALL_F16_FULL + (vec_duplicate:VALL_F16_FULL (match_operand: 1 "aarch64_simd_nonimmediate_operand" "w,?r,Utv")) - (match_operand:VALL_F16 3 "register_operand" "0,0,0") + (match_operand:VALL_F16_FULL 3 "register_operand" "0,0,0") (match_operand:SI 2 "immediate_operand" "i,i,i")))] "TARGET_SIMD" { @@ -1061,14 +1083,14 @@ (define_insn "aarch64_simd_vec_set" ) (define_insn "@aarch64_simd_vec_copy_lane" - [(set (match_operand:VALL_F16 0 "register_operand" "=w") - (vec_merge:VALL_F16 - (vec_duplicate:VALL_F16 + [(set (match_operand:VALL_F16_FULL 0 "register_operand" "=w") + (vec_merge:VALL_F16_FULL + (vec_duplicate:VALL_F16_FULL (vec_select: - (match_operand:VALL_F16 3 "register_operand" "w") + (match_operand:VALL_F16_FULL 3 "register_operand" "w") (parallel [(match_operand:SI 4 "immediate_operand" "i")]))) - (match_operand:VALL_F16 1 "register_operand" "0") + (match_operand:VALL_F16_FULL 1 "register_operand" "0") (match_operand:SI 2 "immediate_operand" "i")))] "TARGET_SIMD" { @@ -1376,7 +1398,7 @@ (define_insn "vec_shr_" ) (define_expand "vec_set" - [(match_operand:VALL_F16 0 "register_operand") + [(match_operand:VALL_F16_FULL 0 "register_operand") (match_operand: 1 "aarch64_simd_nonimmediate_operand") (match_operand:SI 2 "immediate_operand")] "TARGET_SIMD" @@ -3503,7 +3525,7 @@ (define_insn "popcount2" ;; gimple_fold'd to the IFN_REDUC_(MAX|MIN) function. (This is FP smax/smin). (define_expand "reduc__scal_" [(match_operand: 0 "register_operand") - (unspec: [(match_operand:VHSDF 1 "register_operand")] + (unspec: [(match_operand:VHSDF_P 1 "register_operand")] FMAXMINV)] "TARGET_SIMD" { @@ -3518,7 +3540,7 @@ (define_expand "reduc__scal_" (define_expand "reduc__scal_" [(match_operand: 0 "register_operand") - (unspec: [(match_operand:VHSDF 1 "register_operand")] + (unspec: [(match_operand:VHSDF_P 1 "register_operand")] FMAXMINNMV)] "TARGET_SIMD" { @@ -3562,8 +3584,8 @@ (define_insn "aarch64_reduc__internalv2si" ) (define_insn "aarch64_reduc__internal" - [(set (match_operand:VHSDF 0 "register_operand" "=w") - (unspec:VHSDF [(match_operand:VHSDF 1 "register_operand" "w")] + [(set (match_operand:VHSDF_P 0 "register_operand" "=w") + (unspec:VHSDF_P [(match_operand:VHSDF_P 1 "register_operand" "w")] FMAXMINV))] "TARGET_SIMD" "\\t%0, %1." @@ -4208,7 +4230,7 @@ (define_insn "*aarch64_get_lane_zero_extend" (define_insn_and_split "aarch64_get_lane" [(set (match_operand: 0 "aarch64_simd_nonimmediate_operand" "=?r, w, Utv") (vec_select: - (match_operand:VALL_F16 1 "register_operand" "w, w, w") + (match_operand:VALL_F16_FULL 1 "register_operand" "w, w, w") (parallel [(match_operand:SI 2 "immediate_operand" "i, i, i")])))] "TARGET_SIMD" { @@ -7989,7 +8011,7 @@ (define_expand "aarch64_st1" ;; Standard pattern name vec_init. (define_expand "vec_init" - [(match_operand:VALL_F16 0 "register_operand") + [(match_operand:VALL_F16_FULL 0 "register_operand") (match_operand 1 "" "")] "TARGET_SIMD" { @@ -8068,7 +8090,7 @@ (define_insn "aarch64_urecpe" (define_expand "vec_extract" [(match_operand: 0 "aarch64_simd_nonimmediate_operand") - (match_operand:VALL_F16 1 "register_operand") + (match_operand:VALL_F16_FULL 1 "register_operand") (match_operand:SI 2 "immediate_operand")] "TARGET_SIMD" { diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index f05bac713e88ea8c7feaa2367d55bd523ca66f57..1e08f8453688210afe1566092b19b59c9bdd0c97 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -3566,6 +3566,7 @@ aarch64_classify_vector_mode (machine_mode mode) case E_V8BFmode: case E_V4SFmode: case E_V2DFmode: + case E_V2HFmode: return TARGET_SIMD ? VEC_ADVSIMD : 0; default: diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 37d8161a33b1c399d80be82afa67613a087389d4..1df09f7fe2eb35aed96113476541e0faa5393551 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -160,6 +160,10 @@ (define_mode_iterator VDQF [V2SF V4SF V2DF]) (define_mode_iterator VHSDF [(V4HF "TARGET_SIMD_F16INST") (V8HF "TARGET_SIMD_F16INST") V2SF V4SF V2DF]) +;; Advanced SIMD Float modes suitable for pairwise operations. +(define_mode_iterator VHSDF_P [(V4HF "TARGET_SIMD_F16INST") + (V8HF "TARGET_SIMD_F16INST") + V2SF V4SF V2DF (V2HF "TARGET_SIMD_F16INST")]) ;; Advanced SIMD Float modes, and DF. (define_mode_iterator VDQF_DF [V2SF V4SF V2DF DF]) @@ -188,15 +192,23 @@ (define_mode_iterator VDQF_COND [V2SF V2SI V4SF V4SI V2DF V2DI]) (define_mode_iterator VALLF [V2SF V4SF V2DF SF DF]) ;; Advanced SIMD Float modes with 2 elements. -(define_mode_iterator V2F [V2SF V2DF]) +(define_mode_iterator V2F [V2SF V2DF V2HF]) ;; All Advanced SIMD modes on which we support any arithmetic operations. (define_mode_iterator VALL [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF]) -;; All Advanced SIMD modes suitable for moving, loading, and storing. +;; All Advanced SIMD modes suitable for moving, loading, and storing +;; except V2HF. (define_mode_iterator VALL_F16 [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V4HF V8HF V4BF V8BF V2SF V4SF V2DF]) +;; All Advanced SIMD modes suitable for moving, loading, and storing +;; including V2HF +(define_mode_iterator VALL_F16_FULL [V8QI V16QI V4HI V8HI V2SI V4SI V2DI + V4HF V8HF V4BF V8BF V2SF V4SF V2DF + (V2HF "TARGET_SIMD_F16INST")]) + + ;; The VALL_F16 modes except the 128-bit 2-element ones. (define_mode_iterator VALL_F16_NO_V2Q [V8QI V16QI V4HI V8HI V2SI V4SI V4HF V8HF V2SF V4SF]) @@ -1076,7 +1088,7 @@ (define_mode_attr nunits [(V8QI "8") (V16QI "16") (V2SF "2") (V4SF "4") (V1DF "1") (V2DF "2") (DI "1") (DF "1") - (V8DI "8")]) + (V8DI "8") (V2HF "2")]) ;; Map a mode to the number of bits in it, if the size of the mode ;; is constant. @@ -1090,6 +1102,7 @@ (define_mode_attr s [(HF "h") (SF "s") (DF "d") (SI "s") (DI "d")]) ;; Give the length suffix letter for a sign- or zero-extension. (define_mode_attr size [(QI "b") (HI "h") (SI "w")]) +(define_mode_attr sizel [(QI "b") (HI "h") (SI "")]) ;; Give the number of bits in the mode (define_mode_attr sizen [(QI "8") (HI "16") (SI "32") (DI "64")]) @@ -1134,8 +1147,9 @@ (define_mode_attr Vtype [(V8QI "8b") (V16QI "16b") (V2SI "2s") (V4SI "4s") (DI "1d") (DF "1d") (V2DI "2d") (V2SF "2s") - (V4SF "4s") (V2DF "2d") - (V4HF "4h") (V8HF "8h") + (V2HF "2h") (V4SF "4s") + (V2DF "2d") (V4HF "4h") + (V8HF "8h") (V2x8QI "8b") (V2x4HI "4h") (V2x2SI "2s") (V2x1DI "1d") (V2x4HF "4h") (V2x2SF "2s") @@ -1175,9 +1189,10 @@ (define_mode_attr Vmtype [(V8QI ".8b") (V16QI ".16b") (V4HI ".4h") (V8HI ".8h") (V2SI ".2s") (V4SI ".4s") (V2DI ".2d") (V4HF ".4h") - (V8HF ".8h") (V4BF ".4h") - (V8BF ".8h") (V2SF ".2s") - (V4SF ".4s") (V2DF ".2d") + (V8HF ".8h") (V2HF ".2h") + (V4BF ".4h") (V8BF ".8h") + (V2SF ".2s") (V4SF ".4s") + (V2DF ".2d") (DI "") (SI "") (HI "") (QI "") (TI "") (HF "") @@ -1193,7 +1208,7 @@ (define_mode_attr Vmntype [(V8HI ".8b") (V4SI ".4h") (define_mode_attr Vetype [(V8QI "b") (V16QI "b") (V4HI "h") (V8HI "h") (V2SI "s") (V4SI "s") - (V2DI "d") + (V2DI "d") (V2HF "h") (V4HF "h") (V8HF "h") (V2SF "s") (V4SF "s") (V2DF "d") @@ -1285,7 +1300,7 @@ (define_mode_attr Vcwtype [(VNx16QI "b") (VNx8QI "h") (VNx4QI "w") (VNx2QI "d") ;; more accurately. (define_mode_attr stype [(V8QI "b") (V16QI "b") (V4HI "s") (V8HI "s") (V2SI "s") (V4SI "s") (V2DI "d") (V4HF "s") - (V8HF "s") (V2SF "s") (V4SF "s") (V2DF "d") + (V8HF "s") (V2SF "s") (V4SF "s") (V2DF "d") (V2HF "s") (HF "s") (SF "s") (DF "d") (QI "b") (HI "s") (SI "s") (DI "d")]) @@ -1360,8 +1375,8 @@ (define_mode_attr VEL [(V8QI "QI") (V16QI "QI") (V4HF "HF") (V8HF "HF") (V2SF "SF") (V4SF "SF") (DF "DF") (V2DF "DF") - (SI "SI") (HI "HI") - (QI "QI") + (SI "SI") (V2HF "HF") + (QI "QI") (HI "HI") (V4BF "BF") (V8BF "BF") (VNx16QI "QI") (VNx8QI "QI") (VNx4QI "QI") (VNx2QI "QI") (VNx8HI "HI") (VNx4HI "HI") (VNx2HI "HI") @@ -1381,7 +1396,7 @@ (define_mode_attr Vel [(V8QI "qi") (V16QI "qi") (V2SF "sf") (V4SF "sf") (V2DF "df") (DF "df") (SI "si") (HI "hi") - (QI "qi") + (QI "qi") (V2HF "hf") (V4BF "bf") (V8BF "bf") (VNx16QI "qi") (VNx8QI "qi") (VNx4QI "qi") (VNx2QI "qi") (VNx8HI "hi") (VNx4HI "hi") (VNx2HI "hi") @@ -1866,7 +1881,7 @@ (define_mode_attr q [(V8QI "") (V16QI "_q") (V4HF "") (V8HF "_q") (V4BF "") (V8BF "_q") (V2SF "") (V4SF "_q") - (V2DF "_q") + (V2HF "") (V2DF "_q") (QI "") (HI "") (SI "") (DI "") (HF "") (SF "") (DF "") (V2x8QI "") (V2x16QI "_q") (V2x4HI "") (V2x8HI "_q") @@ -1905,6 +1920,7 @@ (define_mode_attr vp [(V8QI "v") (V16QI "v") (V2SI "p") (V4SI "v") (V2DI "p") (V2DF "p") (V2SF "p") (V4SF "v") + (V2HF "p") (V4HF "v") (V8HF "v")]) (define_mode_attr vsi2qi [(V2SI "v8qi") (V4SI "v16qi") diff --git a/gcc/config/arm/types.md b/gcc/config/arm/types.md index 7d0504bdd944e9c0d1b545b0b66a9a1adc808714..3cfbc7a93cca1bea4925853e51d0a147c5722247 100644 --- a/gcc/config/arm/types.md +++ b/gcc/config/arm/types.md @@ -483,6 +483,7 @@ (define_attr "autodetect_type" ; neon_fp_minmax_s_q ; neon_fp_minmax_d ; neon_fp_minmax_d_q +; neon_fp_reduc_add_h ; neon_fp_reduc_add_s ; neon_fp_reduc_add_s_q ; neon_fp_reduc_add_d @@ -1033,6 +1034,7 @@ (define_attr "type" neon_fp_minmax_d,\ neon_fp_minmax_d_q,\ \ + neon_fp_reduc_add_h,\ neon_fp_reduc_add_s,\ neon_fp_reduc_add_s_q,\ neon_fp_reduc_add_d,\ @@ -1257,8 +1259,8 @@ (define_attr "is_neon_type" "yes,no" neon_fp_compare_d, neon_fp_compare_d_q, neon_fp_minmax_s,\ neon_fp_minmax_s_q, neon_fp_minmax_d, neon_fp_minmax_d_q,\ neon_fp_neg_s, neon_fp_neg_s_q, neon_fp_neg_d, neon_fp_neg_d_q,\ - neon_fp_reduc_add_s, neon_fp_reduc_add_s_q, neon_fp_reduc_add_d,\ - neon_fp_reduc_add_d_q, neon_fp_reduc_minmax_s, + neon_fp_reduc_add_h, neon_fp_reduc_add_s, neon_fp_reduc_add_s_q,\ + neon_fp_reduc_add_d, neon_fp_reduc_add_d_q, neon_fp_reduc_minmax_s,\ neon_fp_reduc_minmax_s_q, neon_fp_reduc_minmax_d,\ neon_fp_reduc_minmax_d_q,\ neon_fp_cvt_narrow_s_q, neon_fp_cvt_narrow_d_q,\ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/slp_1.c b/gcc/testsuite/gcc.target/aarch64/sve/slp_1.c index 07d71a63414b1066ea431e287286ad048515711a..8e35e0b574d49913b43c7d8d4f4ba75f127f42e9 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/slp_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/slp_1.c @@ -30,11 +30,9 @@ vec_slp_##TYPE (TYPE *restrict a, TYPE b, TYPE c, int n) \ TEST_ALL (VEC_PERM) /* We should use one DUP for each of the 8-, 16- and 32-bit types, - although we currently use LD1RW for _Float16. We should use two - DUPs for each of the three 64-bit types. */ + We should use two DUPs for each of the three 64-bit types. */ /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.h, [hw]} 2 } } */ -/* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.s, [sw]} 2 } } */ -/* { dg-final { scan-assembler-times {\tld1rw\tz[0-9]+\.s, } 1 } } */ +/* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.s, [sw]} 3 } } */ /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.d, [dx]} 9 } } */ /* { dg-final { scan-assembler-times {\tzip1\tz[0-9]+\.d, z[0-9]+\.d, z[0-9]+\.d\n} 3 } } */ /* { dg-final { scan-assembler-not {\tzip2\t} } } */