From patchwork Sun Jan 16 01:47:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Rodgers X-Patchwork-Id: 50078 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 8D672385841F for ; Sun, 16 Jan 2022 01:49:08 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 8D672385841F DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1642297748; bh=wCSf18SrLX0RI+XMiAYuwVmhAAV+WzOBWd7192W6VCw=; h=Date:Subject:To:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=ns2MeDEfRIl/DYjeiJS7WnHWTWJHByCaEvMxlL5ZSdhQsh2ufh/9BP6423ZGcBbso WEf0sezBuw9F6eyXfRnFwmQamfK7V/o19zWqBJ8ndT8P4iRZwUa1tAqS1oZQDmlLPQ YsyiBfSAybgqDtOKZSlxAyr/5wpINxN2jo7AQqiI= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) by sourceware.org (Postfix) with ESMTPS id 5EDA73858D35 for ; Sun, 16 Jan 2022 01:47:58 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 5EDA73858D35 Received: from mail-oi1-f198.google.com (mail-oi1-f198.google.com [209.85.167.198]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-63-XIcWVL7SPNa_gGCjgVbP9g-1; Sat, 15 Jan 2022 20:47:56 -0500 X-MC-Unique: XIcWVL7SPNa_gGCjgVbP9g-1 Received: by mail-oi1-f198.google.com with SMTP id r11-20020acaa80b000000b002c909592028so9088507oie.9 for ; Sat, 15 Jan 2022 17:47:55 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:from:date:message-id:subject:to; bh=dtR4/323As1MrbW6u71hYA8yl+BaozH447Modb7OM8g=; b=U6f9Frz/pZ1zkMwLzPMJJSHJ/SLhRHoaHR/OC4KTlSRdbbEevR+XKYIINsC/R+Ioz8 ZAYazXw+h/De5NLtjCf0twqaw9JC43eBRg8jfYZp375AfNHcUWOCf69Hon/cvvFHn25P 6TgDoRlTIGSTSPya1Am+Avrbbtymrvwb5F3X33oPbJxPutKokRfxee6sc/VZ3GA9aoBP dqE7Ext0QFDCSBQwqf8XnuAyEF114BZK20X+MI6+l+gmOZgSkQD1D4zbXmcqbJqaERib pOoZTmMHWrkFpr2H65h4xZ1AKojVhXopYBwxfIHmy4nH3jg3GPs6vEQ2UtakhQR4mTEo IRIA== X-Gm-Message-State: AOAM530E4SCzPuYS66dYLCgn49jFWATomxyys0nnqm1rrK3+5fntl9jr dk8MbHrhzDzCdymmqxy3zmFMnd1QTMLTL2GHny57Wi9vrQCbrkmDDWigyD8gJwC1m/nfJlIo68z eswOUyHCWrSgMDZGjNXBGQ1fU5JIfopP2/Q== X-Received: by 2002:aca:ad15:: with SMTP id w21mr17070962oie.132.1642297675304; Sat, 15 Jan 2022 17:47:55 -0800 (PST) X-Google-Smtp-Source: ABdhPJxOqSD75AcQ2mFN1rFkqPUuw+eFt5XAdja3wSoZCVQfZDIJ8E4wCok22qtFUfu3r7/qgKZZmfMAJvVnbA9EeG8= X-Received: by 2002:aca:ad15:: with SMTP id w21mr17070952oie.132.1642297675071; Sat, 15 Jan 2022 17:47:55 -0800 (PST) MIME-Version: 1.0 Date: Sat, 15 Jan 2022 17:47:44 -0800 Message-ID: Subject: [PATCH] Strengthen memory memory order for atomic::wait/notify To: "libstdc++" , gcc Patches X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com X-Spam-Status: No, score=-14.6 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, HTML_MESSAGE, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-Content-Filtered-By: Mailman/MimeDel 2.1.29 X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Thomas Rodgers via Gcc-patches From: Thomas Rodgers Reply-To: Thomas Rodgers Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" This patch updates the memory order of atomic accesses to the waiter's count to match libc++'s usage. It should be backported to GCC11. Tested x86_64-pc-linux-gnu. From f5ed7674f86283db4f4ff49a2cc65d4f852413a1 Mon Sep 17 00:00:00 2001 From: Thomas Rodgers Date: Sat, 15 Jan 2022 17:40:49 -0800 Subject: [PATCH] Strengthen memory memory order for atomic::wait/notify This matches the memory order in libc++. libstdc++-v3/ChangeLog: * libstdc++-v3/include/bits/atomic_wait.h: Change memory order from Acquire/Release with relaxed loads to SeqCst+Release for accesses to the waiter's count. --- libstdc++-v3/include/bits/atomic_wait.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/libstdc++-v3/include/bits/atomic_wait.h b/libstdc++-v3/include/bits/atomic_wait.h index 05cf0013d2a..d7de0d7eb9e 100644 --- a/libstdc++-v3/include/bits/atomic_wait.h +++ b/libstdc++-v3/include/bits/atomic_wait.h @@ -209,18 +209,18 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION void _M_enter_wait() noexcept - { __atomic_fetch_add(&_M_wait, 1, __ATOMIC_ACQ_REL); } + { __atomic_fetch_add(&_M_wait, 1, __ATOMIC_SEQ_CST); } void _M_leave_wait() noexcept - { __atomic_fetch_sub(&_M_wait, 1, __ATOMIC_ACQ_REL); } + { __atomic_fetch_sub(&_M_wait, 1, __ATOMIC_RELEASE); } bool _M_waiting() const noexcept { __platform_wait_t __res; - __atomic_load(&_M_wait, &__res, __ATOMIC_ACQUIRE); - return __res > 0; + __atomic_load(&_M_wait, &__res, __ATOMIC_SEQ_CST); + return __res != 0; } void @@ -258,7 +258,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION __platform_wait(__addr, __old); #else __platform_wait_t __val; - __atomic_load(__addr, &__val, __ATOMIC_RELAXED); + __atomic_load(__addr, &__val, __ATOMIC_SEQ_CST); if (__val == __old) { lock_guard __l(_M_mtx); @@ -309,7 +309,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION { if (_M_laundered()) { - __atomic_fetch_add(_M_addr, 1, __ATOMIC_ACQ_REL); + __atomic_fetch_add(_M_addr, 1, __ATOMIC_SEQ_CST); __all = true; } _M_w._M_notify(_M_addr, __all, __bare); -- 2.31.1