From patchwork Thu Nov 18 14:24:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 47886 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 84DA23857C5F for ; Thu, 18 Nov 2021 14:26:08 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 84DA23857C5F DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1637245568; bh=8/+JbrSSdHi8HuEXWcIFZ5/z7dShdQH/3UnBtsQxztk=; h=References:In-Reply-To:Date:Subject:To:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=kPSRWtLvi97J2J6T5dwkc2+ydaiw40mAW7LKSvP6SK8nSxm7D70REc3EKBLvGDVKW aFQ+UmNRUm11JISVW/kF0DugbxF5e4mAQugVDsEplsdbcwOHE5JWB9AjkjX5XJzy+3 89h8VWqVoeqhQSjlyG2nvACs2U4RPPVAQnxsiGFM= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pf1-x430.google.com (mail-pf1-x430.google.com [IPv6:2607:f8b0:4864:20::430]) by sourceware.org (Postfix) with ESMTPS id DC9063857817 for ; Thu, 18 Nov 2021 14:24:51 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org DC9063857817 Received: by mail-pf1-x430.google.com with SMTP id z6so6159597pfe.7 for ; Thu, 18 Nov 2021 06:24:51 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=8/+JbrSSdHi8HuEXWcIFZ5/z7dShdQH/3UnBtsQxztk=; b=q5UXbeNOElEzTGA30viq1KOmYtVi9sCfG/WLSU/xr/b0iVWWFwHi4caYD9XmJ/GGBt meQXWQajWxS91R2dzHdwjWJDqa8w7teRZa+8GgczUmE3oSFkbcC51m9Iu8fpasZV8hb0 zl6CSYgoUtUL+AB7sRiEoAUWaxgXyl7yyl8Ow4IY+qXvHHJz/1fHwUkotNuu0tolnZT7 imcbA+KmadWTN83pCzObC4+zu0wCEWKjkWs/pCPI/BXm1njTna410nMwSmxvA+wZzwsP c8aMJzG5qPozF0dGFdkcKkeIvIZ3UmHK0xgB7z5t16RzfQiveBGD+WzHeVz/CQgEeSbH 8uCQ== X-Gm-Message-State: AOAM532I1UhNt53VGDEFM5U2Yl3kJPvyVlWdpnIP3Yl/kkD8d6LaajhM q3XFSJOXnb3MyVFY5f7P7/eqygkyWZ9qtBYolRE= X-Google-Smtp-Source: ABdhPJwXu23d77/TZD33/skqiCxD+qs+VkCZpd/f9xubYuJbK3NBqXQU22nmswglNe57pn3VOxtjYnFc2VLc5gp7+Go= X-Received: by 2002:a05:6a00:2351:b0:47b:d092:d2e4 with SMTP id j17-20020a056a00235100b0047bd092d2e4mr55268697pfj.76.1637245490937; Thu, 18 Nov 2021 06:24:50 -0800 (PST) MIME-Version: 1.0 References: <20211117134741.212383-1-hjl.tools@gmail.com> In-Reply-To: Date: Thu, 18 Nov 2021 06:24:15 -0800 Message-ID: Subject: [PATCH v3] x86: Add -mindirect-branch-cs-prefix To: Uros Bizjak X-Spam-Status: No, score=-3029.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "H.J. Lu via Gcc-patches" From: "H.J. Lu" Reply-To: "H.J. Lu" Cc: "gcc-patches@gcc.gnu.org" Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" On Thu, Nov 18, 2021 at 12:25 AM Uros Bizjak wrote: > > On Wed, Nov 17, 2021 at 2:47 PM H.J. Lu wrote: > > > > Add -mindirect-branch-cs-prefix to add CS prefix to call and jmp to thunk > > via r8-r15 registers when converting indirect call and jump to increase > > the instruction length to 6, allowing the non-thunk form to be inlined. > > > > gcc/ > > > > PR target/102952 > > * config/i386/i386.c (ix86_output_jmp_thunk_or_indirect): Emit > > CS prefix for -mindirect-branch-cs-prefix. > > (ix86_output_indirect_branch_via_reg): Likewise. > > * config/i386/i386.opt: Add -mindirect-branch-cs-prefix. > > * doc/invoke.texi: Document -mindirect-branch-cs-prefix. > > > > gcc/testsuite/ > > > > PR target/102952 > > * gcc.target/i386/indirect-thunk-cs-prefix-1.c: New test. > > * gcc.target/i386/indirect-thunk-cs-prefix-2.c: Likewise. > > It is hard for me to parse the description, both in the commit message > and in the option description and documentation. Can you please reword > them to be more comprehensible? > > Here is the v3 patch with updated description. OK for master? Thanks. From ed12d22089b7ee75f20e504f9e7c898dd2b92215 Mon Sep 17 00:00:00 2001 From: "H.J. Lu" Date: Wed, 27 Oct 2021 06:27:15 -0700 Subject: [PATCH v3] x86: Add -mindirect-branch-cs-prefix Add -mindirect-branch-cs-prefix to add CS prefix to call and jmp to indirect thunk with branch target in r8-r15 registers so that the call and jmp instruction length is 6 bytes to allow them to be replaced with "lfence; call *%r8-r15" or "lfence; jmp *%r8-r15" at run-time. gcc/ PR target/102952 * config/i386/i386.c (ix86_output_jmp_thunk_or_indirect): Emit CS prefix for -mindirect-branch-cs-prefix. (ix86_output_indirect_branch_via_reg): Likewise. * config/i386/i386.opt: Add -mindirect-branch-cs-prefix. * doc/invoke.texi: Document -mindirect-branch-cs-prefix. gcc/testsuite/ PR target/102952 * gcc.target/i386/indirect-thunk-cs-prefix-1.c: New test. * gcc.target/i386/indirect-thunk-cs-prefix-2.c: Likewise. --- gcc/config/i386/i386.c | 6 ++++++ gcc/config/i386/i386.opt | 4 ++++ gcc/doc/invoke.texi | 10 +++++++++- .../gcc.target/i386/indirect-thunk-cs-prefix-1.c | 14 ++++++++++++++ .../gcc.target/i386/indirect-thunk-cs-prefix-2.c | 15 +++++++++++++++ 5 files changed, 48 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/i386/indirect-thunk-cs-prefix-1.c create mode 100644 gcc/testsuite/gcc.target/i386/indirect-thunk-cs-prefix-2.c diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index c246c8736f5..7fe271b1b94 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -15982,6 +15982,9 @@ ix86_output_jmp_thunk_or_indirect (const char *thunk_name, const int regno) { if (thunk_name != NULL) { + if (REX_INT_REGNO_P (regno) + && ix86_indirect_branch_cs_prefix) + fprintf (asm_out_file, "\tcs\n"); fprintf (asm_out_file, "\tjmp\t"); assemble_name (asm_out_file, thunk_name); putc ('\n', asm_out_file); @@ -16031,6 +16034,9 @@ ix86_output_indirect_branch_via_reg (rtx call_op, bool sibcall_p) { if (thunk_name != NULL) { + if (REX_INT_REGNO_P (regno) + && ix86_indirect_branch_cs_prefix) + fprintf (asm_out_file, "\tcs\n"); fprintf (asm_out_file, "\tcall\t"); assemble_name (asm_out_file, thunk_name); putc ('\n', asm_out_file); diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt index 2b6d8aab101..3e67c537bb7 100644 --- a/gcc/config/i386/i386.opt +++ b/gcc/config/i386/i386.opt @@ -1076,6 +1076,10 @@ Enum(indirect_branch) String(thunk-inline) Value(indirect_branch_thunk_inline) EnumValue Enum(indirect_branch) String(thunk-extern) Value(indirect_branch_thunk_extern) +mindirect-branch-cs-prefix +Target Var(ix86_indirect_branch_cs_prefix) Init(0) +Add CS prefix to call and jmp to indirect thunk with branch target in r8-r15 registers. + mindirect-branch-register Target Var(ix86_indirect_branch_register) Init(0) Force indirect call and jump via register. diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index d62ec08150e..5fed1dd6a31 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1427,7 +1427,8 @@ See RS/6000 and PowerPC Options. -mstack-protector-guard-symbol=@var{symbol} @gol -mgeneral-regs-only -mcall-ms2sysv-xlogues -mrelax-cmpxchg-loop @gol -mindirect-branch=@var{choice} -mfunction-return=@var{choice} @gol --mindirect-branch-register -mharden-sls=@var{choice} -mneeded} +-mindirect-branch-register -mharden-sls=@var{choice} @gol +-mindirect-branch-cs-prefix -mneeded} @emph{x86 Windows Options} @gccoptlist{-mconsole -mcygwin -mno-cygwin -mdll @gol @@ -32416,6 +32417,13 @@ hardening. @samp{return} enables SLS hardening for function return. @samp{indirect-branch} enables SLS hardening for indirect branch. @samp{all} enables all SLS hardening. +@item -mindirect-branch-cs-prefix +@opindex mindirect-branch-cs-prefix +Add CS prefix to call and jmp to indirect thunk with branch target in +r8-r15 registers so that the call and jmp instruction length is 6 bytes +to allow them to be replaced with @samp{lfence; call *%r8-r15} or +@samp{lfence; jmp *%r8-r15} at run-time. + @end table These @samp{-m} switches are supported in addition to the above diff --git a/gcc/testsuite/gcc.target/i386/indirect-thunk-cs-prefix-1.c b/gcc/testsuite/gcc.target/i386/indirect-thunk-cs-prefix-1.c new file mode 100644 index 00000000000..db2f3416823 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/indirect-thunk-cs-prefix-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -ffixed-rax -ffixed-rbx -ffixed-rcx -ffixed-rdx -ffixed-rdi -ffixed-rsi -mindirect-branch-cs-prefix -mindirect-branch=thunk-extern" } */ +/* { dg-additional-options "-fno-pic" { target { ! *-*-darwin* } } } */ + +extern void (*fptr) (void); + +void +foo (void) +{ + fptr (); +} + +/* { dg-final { scan-assembler-times "jmp\[ \t\]+_?__x86_indirect_thunk_r\[0-9\]+" 1 } } */ +/* { dg-final { scan-assembler-times "\tcs" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/indirect-thunk-cs-prefix-2.c b/gcc/testsuite/gcc.target/i386/indirect-thunk-cs-prefix-2.c new file mode 100644 index 00000000000..adfc39a49d4 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/indirect-thunk-cs-prefix-2.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -ffixed-rax -ffixed-rbx -ffixed-rcx -ffixed-rdx -ffixed-rdi -ffixed-rsi -mindirect-branch-cs-prefix -mindirect-branch=thunk-extern" } */ +/* { dg-additional-options "-fno-pic" { target { ! *-*-darwin* } } } */ + +extern void (*bar) (void); + +int +foo (void) +{ + bar (); + return 0; +} + +/* { dg-final { scan-assembler-times "call\[ \t\]+_?__x86_indirect_thunk_r\[0-9\]+" 1 } } */ +/* { dg-final { scan-assembler-times "\tcs" 1 } } */ -- 2.33.1