From patchwork Fri Dec 24 16:12:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 49247 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A8176385842A for ; Fri, 24 Dec 2021 16:12:47 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org A8176385842A DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1640362367; bh=louCYK/CWGekf9DTpiwOmAPruOMPrqjV4ahO2gu01t4=; h=Date:Subject:To:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=qaOY9t59vQpfT7y83hn6EZZGXn7R3g9DR8zW6lI5ldsDn7CvjNmSy5VHPzY5kzr8f UrevqUVJEpu1Tag5wWv/+UlXSML0JGo9bO7sHeIeNkP6XXwBBBv97Uq+jc9O2YH8Ov pXonGH32iVujiEy23tITmR+xhWV4UDI3fSJz2PKE= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-qt1-x829.google.com (mail-qt1-x829.google.com [IPv6:2607:f8b0:4864:20::829]) by sourceware.org (Postfix) with ESMTPS id 555613858C27 for ; Fri, 24 Dec 2021 16:12:18 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 555613858C27 Received: by mail-qt1-x829.google.com with SMTP id f9so7963956qtk.4 for ; Fri, 24 Dec 2021 08:12:18 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:from:date:message-id:subject:to; bh=louCYK/CWGekf9DTpiwOmAPruOMPrqjV4ahO2gu01t4=; b=BKFu3fdKmgiHSjbCAaVi5f4t6jvpPmlekVBztgqcG+if14wWaBtYTLvJeWZD05vNyu GcU1qjOPt7WkM2j8Di8Vmd4yAAUXUEnlxOGUbOLCYogLAcRSDsZ/PovA0J4ULchDjdqY 0AGGKlBrYgBtfOEOhM/rmUcspEy0WXbZx0gwLk8hLhGUzUX+3Bw0F6SRxqrVLG8mowBU 1T4twPA5h/dGaazEg+4fwW9IbLOZ4WMchuR9Ldl9BxKqV/U4v11lFljuvLc1qtoCjqj+ c+N59PZd0GyZ5lnOsjdT5BTda7kny+B/LHFaGPpe+h1+EZFjDOQg9k0ETWB7pU3vb7Va Fo8A== X-Gm-Message-State: AOAM530rf/l+8+U33sEOsBkLtyiHr9mJQC3RU2+Ka7E4fFcHyUCWd/8V zizF9uhbmpUQ5u8cFZh7V95kxq278lHW7sagn3Bm4x236jR3jw== X-Google-Smtp-Source: ABdhPJxTGjPX3Nbk/p7BKLtSxkzt+98wFkmoPFtYkoFpNqptCaUmEKrMkeQcLa6KYPbRDMGKYLQJYTDu/7R3aBdHsog= X-Received: by 2002:a05:622a:24a:: with SMTP id c10mr6051903qtx.209.1640362337733; Fri, 24 Dec 2021 08:12:17 -0800 (PST) MIME-Version: 1.0 Date: Fri, 24 Dec 2021 17:12:06 +0100 Message-ID: Subject: [PATCH] i386: Add V2SFmode DIV insn pattern [PR95046, PR103797] To: "gcc-patches@gcc.gnu.org" X-Spam-Status: No, score=-8.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Uros Bizjak via Gcc-patches From: Uros Bizjak Reply-To: Uros Bizjak Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Use V4SFmode "DIVPS X,Y" with [y0, y1, 1.0f, 1.0f] as a divisor to avoid division by zero. 2021-12-24 Uroš Bizjak gcc/ChangeLog: PR target/95046 PR target/103797 * config/i386/mmx.md (divv2sf3): New instruction pattern. gcc/testsuite/ChangeLog: PR target/95046 PR target/103797 * gcc.target/i386/pr95046-1.c (test_div): Add. (dg-options): Add -mno-recip. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Pushed to master. Uros. diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 6c5cbcfa52c..5a5755654c2 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -523,6 +523,26 @@ (set_attr "prefix" "*,orig,vex") (set_attr "mode" "V2SF,V4SF,V4SF")]) +(define_expand "divv2sf3" + [(set (match_operand:V2SF 0 "register_operand") + (div:V2SF (match_operand:V2SF 1 "register_operand") + (match_operand:V2SF 2 "register_operand")))] + "TARGET_MMX_WITH_SSE" +{ + rtx op0 = lowpart_subreg (V4SFmode, operands[0], + GET_MODE (operands[0])); + rtx op1 = lowpart_subreg (V4SFmode, operands[1], + GET_MODE (operands[1])); + rtx op2 = gen_rtx_VEC_CONCAT (V4SFmode, operands[2], + force_reg (V2SFmode, CONST1_RTX (V2SFmode))); + rtx tmp = gen_reg_rtx (V4SFmode); + + emit_insn (gen_rtx_SET (tmp, op2)); + + emit_insn (gen_divv4sf3 (op0, op1, tmp)); + DONE; +}) + (define_expand "mmx_v2sf3" [(set (match_operand:V2SF 0 "register_operand") (smaxmin:V2SF diff --git a/gcc/testsuite/gcc.target/i386/pr95046-1.c b/gcc/testsuite/gcc.target/i386/pr95046-1.c index bcc8bb5bfab..2a0e6db5fa5 100644 --- a/gcc/testsuite/gcc.target/i386/pr95046-1.c +++ b/gcc/testsuite/gcc.target/i386/pr95046-1.c @@ -1,6 +1,6 @@ /* PR target/95046 */ /* { dg-do compile { target { ! ia32 } } } */ -/* { dg-options "-O3 -ffast-math -msse2" } */ +/* { dg-options "-O3 -ffast-math -msse2 -mno-recip" } */ float r[2], a[2], b[2]; @@ -32,6 +32,15 @@ test_mult (void) /* { dg-final { scan-assembler "\tv?mulps" } } */ +void +test_div (void) +{ + for (int i = 0; i < 2; i++) + r[i] = a[i] / b[i]; +} + +/* { dg-final { scan-assembler "\tv?divps" } } */ + void test_min (void) {