From patchwork Wed Nov 17 19:34:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 47845 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 90ADE385AC31 for ; Wed, 17 Nov 2021 19:35:13 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 90ADE385AC31 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1637177713; bh=z/Gn/JQq1Ht3ZOc9+DFvuWqU5rg9EOF/yqfwfHnyHDg=; h=Date:Subject:To:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=qMoXm7j5AZl1vUtdU+kwK44AQ2kEVSw8meAIAR8C+mQZATpPvQ4j97GG6fvCMsZNx cj8Xb34DX8kzaOD+tojgRojb8VRf0T6LI7kNti2v+t04A4xlvznQQlk1v/PYhqQroL gIVCFsiEI7QTkgieB2uf492vooC4V5HXG+/ELeFg= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-qk1-x732.google.com (mail-qk1-x732.google.com [IPv6:2607:f8b0:4864:20::732]) by sourceware.org (Postfix) with ESMTPS id 5569B385AC0A for ; Wed, 17 Nov 2021 19:34:44 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 5569B385AC0A Received: by mail-qk1-x732.google.com with SMTP id 132so3736413qkj.11 for ; Wed, 17 Nov 2021 11:34:44 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:from:date:message-id:subject:to; bh=z/Gn/JQq1Ht3ZOc9+DFvuWqU5rg9EOF/yqfwfHnyHDg=; b=jDyepJLuds+/iTQElmPzqf4pJKM5bbNOSeP1fFbVlXwiXQ+hXfCPhyhVXYDJ9MYjfW az9UNTBkMuiWL3zTj1iLgrRp6EZ8djO9zfzIcla0oH3sseHjtYfKt3yeUv2kx4LPrffv ckHsEMenX39s0hdlGoq+IEkh2Ljm2yvBCTOdLNBw1GbRkRn3vNBHNsrbQiRdZtOBkxya J3bnHwHX+HLUQnrZ4pCNQIFF5AYTL80jgFfhQYPHTtAdPETTJS5sgt05AikzYf8BJmze 2sKEe12xZ4JWl7MFhOM8YWCUb0zu3TaV/N0t39fMA2e8iFyIG5pw4MsoV6GUx4nO8LDi vkTQ== X-Gm-Message-State: AOAM5301jwkfB/2/sHtARZh1hgoAgT0gsOTK68spx484nu4J95d0Jndr crhIyxDiBG6hJggc8nK9nHNp0sTRou5ifrnObegupQOR0g9jkA== X-Google-Smtp-Source: ABdhPJyh/d7cBNICZzfgkUxu6e9YHOB8VFgA13AWDbp54QOO94ty+wxm7bhlfgYTsYLSLiiPiNiNIlFbDNwxPTLhRfM= X-Received: by 2002:a37:e219:: with SMTP id g25mr15453162qki.373.1637177683660; Wed, 17 Nov 2021 11:34:43 -0800 (PST) MIME-Version: 1.0 Date: Wed, 17 Nov 2021 20:34:32 +0100 Message-ID: Subject: [PATCH] i386: Introduce LEGACY_SSE_REGNO_P predicate To: "gcc-patches@gcc.gnu.org" X-Spam-Status: No, score=-8.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Uros Bizjak via Gcc-patches From: Uros Bizjak Reply-To: Uros Bizjak Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Introduce LEGACY_SSE_REGNO_P predicate to simplify a couple of places. No functional changes. 2021-11-17 Uroš Bizjak gcc/ChangeLog: * config/i386/i386.h (LEGACY_SSE_REGNO_P): New predicate. (SSE_REGNO_P): Use LEGACY_SSE_REGNO_P predicate. * config/i386/i386.c (zero_all_vector_registers): Use LEGACY_SSE_REGNO_P predicate. (ix86_register_priority): Use REX_INT_REGNO_P, REX_SSE_REGNO_P and EXT_REG_SSE_REGNO_P predicates. (ix86_hard_regno_call_part_clobbered): Use REX_SSE_REGNO_P and LEGACY_SSE_REGNO_P predicates. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Pushed to master. Uros. diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 73c4d5115bb..0c5439dc7a7 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -3665,7 +3665,7 @@ zero_all_vector_registers (HARD_REG_SET need_zeroed_hardregs) return NULL; for (unsigned int regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) - if ((IN_RANGE (regno, FIRST_SSE_REG, LAST_SSE_REG) + if ((LEGACY_SSE_REGNO_P (regno) || (TARGET_64BIT && (REX_SSE_REGNO_P (regno) || (TARGET_AVX512F && EXT_REX_SSE_REGNO_P (regno))))) @@ -19089,15 +19089,13 @@ ix86_register_priority (int hard_regno) return 0; if (hard_regno == BP_REG) return 1; - /* New x86-64 int registers result in bigger code size. Discourage - them. */ - if (IN_RANGE (hard_regno, FIRST_REX_INT_REG, LAST_REX_INT_REG)) + /* New x86-64 int registers result in bigger code size. Discourage them. */ + if (REX_INT_REGNO_P (hard_regno)) return 2; - /* New x86-64 SSE registers result in bigger code size. Discourage - them. */ - if (IN_RANGE (hard_regno, FIRST_REX_SSE_REG, LAST_REX_SSE_REG)) + /* New x86-64 SSE registers result in bigger code size. Discourage them. */ + if (REX_SSE_REGNO_P (hard_regno)) return 2; - if (IN_RANGE (hard_regno, FIRST_EXT_REX_SSE_REG, LAST_EXT_REX_SSE_REG)) + if (EXT_REX_SSE_REGNO_P (hard_regno)) return 1; /* Usage of AX register results in smaller code. Prefer it. */ if (hard_regno == AX_REG) @@ -19974,9 +19972,8 @@ ix86_hard_regno_call_part_clobbered (unsigned int abi_id, unsigned int regno, /* Special ABI for vzeroupper which only clobber higher part of sse regs. */ if (abi_id == ABI_VZEROUPPER) return (GET_MODE_SIZE (mode) > 16 - && ((TARGET_64BIT - && (IN_RANGE (regno, FIRST_REX_SSE_REG, LAST_REX_SSE_REG))) - || (IN_RANGE (regno, FIRST_SSE_REG, LAST_SSE_REG)))); + && ((TARGET_64BIT && REX_SSE_REGNO_P (regno)) + || LEGACY_SSE_REGNO_P (regno))); return SSE_REGNO_P (regno) && GET_MODE_SIZE (mode) > 16; } diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index e35c79c192c..2fda1e0686e 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -1409,10 +1409,13 @@ enum reg_class #define SSE_REG_P(X) (REG_P (X) && SSE_REGNO_P (REGNO (X))) #define SSE_REGNO_P(N) \ - (IN_RANGE ((N), FIRST_SSE_REG, LAST_SSE_REG) \ + (LEGACY_SSE_REGNO_P (N) \ || REX_SSE_REGNO_P (N) \ || EXT_REX_SSE_REGNO_P (N)) +#define LEGACY_SSE_REGNO_P(N) \ + IN_RANGE ((N), FIRST_SSE_REG, LAST_SSE_REG) + #define REX_SSE_REGNO_P(N) \ IN_RANGE ((N), FIRST_REX_SSE_REG, LAST_REX_SSE_REG)