From patchwork Fri Jan 14 15:09:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 50035 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9C3F53835C20 for ; Fri, 14 Jan 2022 15:10:04 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 9C3F53835C20 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1642173004; bh=b29lVE+xScpduV07Pf0aIYgeGGCBiyUrQxDGrP4nxdU=; h=Date:Subject:To:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=HSbAGHjBZolN5+CZVfsjU5hThH/ZJS1B1FEbLGjn2pIYP6KjdBvwHSQ5pI1gJbiSl 0hRsU1S8FDkyxJye0/mu8W+VRzRmP4X8aE6XoXlovmyPxKzbu+kEdJ1hwQKPBUcnl9 gtaL/9X+nQrddgdNE+PbrU+QCuLzfseVxCF52n1w= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-qt1-x82b.google.com (mail-qt1-x82b.google.com [IPv6:2607:f8b0:4864:20::82b]) by sourceware.org (Postfix) with ESMTPS id 3BCAA3858D35 for ; Fri, 14 Jan 2022 15:09:35 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 3BCAA3858D35 Received: by mail-qt1-x82b.google.com with SMTP id bp39so10907424qtb.6 for ; Fri, 14 Jan 2022 07:09:35 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:from:date:message-id:subject:to; bh=b29lVE+xScpduV07Pf0aIYgeGGCBiyUrQxDGrP4nxdU=; b=Y2v6LqgcI3g40MbA9phyw2VcLCBSODVgqALzNm2cLufONGctMUWXX7bCWZWtSOQNVg YlJz4k9Ca5Ns6QhOCxAmkCWQfXO6fAeG+GtaHVnGlbHzKuhwjGl6BFiOIddIqxbg9nzq 5vHCQfs/sWS/6BPeSpFBaW6MAJIvRmygZb/IQaS/EamgA3lI+hhgDQfG4gBal6AltmZy loFfz4Xw+1bELItNiXybI8umq7ULuMlH/5Mx3iXzvNpPsnXGZwbp5j8VDJRZoG5XcRS/ RATG+O290qaFNBJPuF6Bkn8QW+Ah+YHd/nI1axGecmtKIVH3SAknA3vvIOe9aKEJDU4n Ls9Q== X-Gm-Message-State: AOAM531y1/adX2S8Z+uNyC1ITlZPGIZzAJ7Ex6FtG5AmI/dp+zUIt/oW qP5+AQAd00VJH86RhXU+ogS8XuZGOQjdYpCU2EK55eYrxoR1AA== X-Google-Smtp-Source: ABdhPJxWOYVmWiVky+bjVRQ7Gne6FxBM2ohSVaFbI3jJIsEk9bnZVmR3g9lPa+CtEmblB5DDxWQ4hPtS0pdNCS5LnxQ= X-Received: by 2002:ac8:5e4a:: with SMTP id i10mr7829716qtx.569.1642172974506; Fri, 14 Jan 2022 07:09:34 -0800 (PST) MIME-Version: 1.0 Date: Fri, 14 Jan 2022 16:09:23 +0100 Message-ID: Subject: [PATCH] i386: Mark some of strict_low_part insn constraints earlyclobbered To: "gcc-patches@gcc.gnu.org" X-Spam-Status: No, score=-8.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Uros Bizjak via Gcc-patches From: Uros Bizjak Reply-To: Uros Bizjak Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" While there is practically impossible that input registers are matched with in-out register, better mark the output operand of the split alternative as earlyclobbered - we do output early to the output operand when the insn is split. 2022-01-14 Uroš Bizjak gcc/ChangeLog: * config/i386/i386.md (*add_1_slp"): Mark alternative 1 output operand earlyclobbered. (*sub_1_slp): Ditto. (*and_1_slp): Ditto. (*_1_slp): Ditto. (*neg_1_slp): Ditto. (*one_cmpl_1_slp): Ditto. (*ashl3_1_slp): Ditto. (*3_1_slp): Ditto. (*3_1_slp): Ditto. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Pushed to master. Uros. diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index c2acb1dbd90..bd965df79df 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -5902,7 +5902,7 @@ ;; Alternative 1 is needed to work around LRA limitation, see PR82524. (define_insn_and_split "*add_1_slp" - [(set (strict_low_part (match_operand:SWI12 0 "register_operand" "+,")) + [(set (strict_low_part (match_operand:SWI12 0 "register_operand" "+,&")) (plus:SWI12 (match_operand:SWI12 1 "nonimmediate_operand" "%0,!") (match_operand:SWI12 2 "general_operand" "mn,mn"))) (clobber (reg:CC FLAGS_REG))] @@ -6856,7 +6856,7 @@ ;; Alternative 1 is needed to work around LRA limitation, see PR82524. (define_insn_and_split "*sub_1_slp" - [(set (strict_low_part (match_operand:SWI12 0 "register_operand" "+,")) + [(set (strict_low_part (match_operand:SWI12 0 "register_operand" "+,&")) (minus:SWI12 (match_operand:SWI12 1 "register_operand" "0,!") (match_operand:SWI12 2 "general_operand" "mn,mn"))) (clobber (reg:CC FLAGS_REG))] @@ -9905,7 +9905,7 @@ ;; Alternative 1 is needed to work around LRA limitation, see PR82524. (define_insn_and_split "*and_1_slp" - [(set (strict_low_part (match_operand:SWI12 0 "register_operand" "+,")) + [(set (strict_low_part (match_operand:SWI12 0 "register_operand" "+,&")) (and:SWI12 (match_operand:SWI12 1 "nonimmediate_operand" "%0,!") (match_operand:SWI12 2 "general_operand" "mn,mn"))) (clobber (reg:CC FLAGS_REG))] @@ -10543,7 +10543,7 @@ ;; Alternative 1 is needed to work around LRA limitation, see PR82524. (define_insn_and_split "*_1_slp" - [(set (strict_low_part (match_operand:SWI12 0 "register_operand" "+,")) + [(set (strict_low_part (match_operand:SWI12 0 "register_operand" "+,&")) (any_or:SWI12 (match_operand:SWI12 1 "nonimmediate_operand" "%0,!") (match_operand:SWI12 2 "general_operand" "mn,mn"))) (clobber (reg:CC FLAGS_REG))] @@ -10897,7 +10897,7 @@ ;; Alternative 1 is needed to work around LRA limitation, see PR82524. (define_insn_and_split "*neg_1_slp" - [(set (strict_low_part (match_operand:SWI12 0 "register_operand" "+,")) + [(set (strict_low_part (match_operand:SWI12 0 "register_operand" "+,&")) (neg:SWI12 (match_operand:SWI12 1 "register_operand" "0,!"))) (clobber (reg:CC FLAGS_REG))] "!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)" @@ -11490,7 +11490,7 @@ ;; Alternative 1 is needed to work around LRA limitation, see PR82524. (define_insn_and_split "*one_cmpl_1_slp" - [(set (strict_low_part (match_operand:SWI12 0 "register_operand" "+,")) + [(set (strict_low_part (match_operand:SWI12 0 "register_operand" "+,&")) (not:SWI12 (match_operand:SWI12 1 "register_operand" "0,!")))] "!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)" "@ @@ -12186,7 +12186,7 @@ ;; Alternative 1 is needed to work around LRA limitation, see PR82524. (define_insn_and_split "*ashl3_1_slp" - [(set (strict_low_part (match_operand:SWI12 0 "register_operand" "+,")) + [(set (strict_low_part (match_operand:SWI12 0 "register_operand" "+,&")) (ashift:SWI12 (match_operand:SWI12 1 "register_operand" "0,!") (match_operand:QI 2 "nonmemory_operand" "cI,cI"))) (clobber (reg:CC FLAGS_REG))] @@ -13063,7 +13063,7 @@ ;; Alternative 1 is needed to work around LRA limitation, see PR82524. (define_insn_and_split "*3_1_slp" - [(set (strict_low_part (match_operand:SWI12 0 "register_operand" "+,")) + [(set (strict_low_part (match_operand:SWI12 0 "register_operand" "+,&")) (any_shiftrt:SWI12 (match_operand:SWI12 1 "register_operand" "0,!") (match_operand:QI 2 "nonmemory_operand" "cI,cI"))) (clobber (reg:CC FLAGS_REG))] @@ -13607,7 +13607,7 @@ ;; Alternative 1 is needed to work around LRA limitation, see PR82524. (define_insn_and_split "*3_1_slp" - [(set (strict_low_part (match_operand:SWI12 0 "register_operand" "+,")) + [(set (strict_low_part (match_operand:SWI12 0 "register_operand" "+,&")) (any_rotate:SWI12 (match_operand:SWI12 1 "register_operand" "0,!") (match_operand:QI 2 "nonmemory_operand" "cI,cI"))) (clobber (reg:CC FLAGS_REG))]