From patchwork Mon Jan 10 20:04:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 49811 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C4C44389043C for ; Mon, 10 Jan 2022 20:04:59 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org C4C44389043C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1641845099; bh=IEc0SvdyBGBUxsG7LPuXhZtm7TyjhQER0JZy9n8NAkA=; h=Date:Subject:To:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=r0MWsXOhvjjswnVdXsY5zzh9u9WJ7OwefmI6Hf7l7RuGn+WqbYY4SwvT9PLKknClF RlTKMqFNpN8q3eHJjEls2MO/0ZrGZFwsmIpf6Sm0Y/6YdhBIe6W7T+hyYIFdduddab YKDWw1S0ponhotfZaoSbbhDh3enU8Msir6sJcWug= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-qk1-x72b.google.com (mail-qk1-x72b.google.com [IPv6:2607:f8b0:4864:20::72b]) by sourceware.org (Postfix) with ESMTPS id 303D03889804 for ; Mon, 10 Jan 2022 20:04:30 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 303D03889804 Received: by mail-qk1-x72b.google.com with SMTP id b85so16336124qkc.1 for ; Mon, 10 Jan 2022 12:04:30 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:from:date:message-id:subject:to; bh=IEc0SvdyBGBUxsG7LPuXhZtm7TyjhQER0JZy9n8NAkA=; b=Vo8X49BTOkqxcJcmDQRMp/VyyWLmXOvtNow8hlg8x3TOnbQHWrsUNDd8LJ/RElGhBl P8nRd1l4mzlXh4WORGia91bgE/r9GYCuw45xwEGP+7pxlYodRZXz6/sqHUv8FuuOZN2y mxioLuSLOlGisvGJRbWRvhic85eK4K+OEOCigpLdOb5/KbcbGnjlzEHPdQb2rUZfhQgh MHmF56aQTt2ZxmRgYVbnDaKqkrOdaKAiNnQH2zucf5g07mt3DvTkWAhW+QyCc+xwAVxf +R/UPMFNKLirxIX0HlQ7r3TE4STkRSLxNJnN2BT9V2Y6f4Xr8uSgY6vs6lm7kEo87InH m+fg== X-Gm-Message-State: AOAM530m7HOx9qTLkiI38BgoEgeil6V7P35BZ8iTV34idlO4p0PBTKiV Fxga6V5HrKMa1Z2IiSg1mJ3lQjUVWnJqeTvq+9WjVNWELNYuyQ== X-Google-Smtp-Source: ABdhPJyg8rnjtRIGy3NjIEuCy5++IxudEGanlix/9YaknyhISbUCAXb2l0U4R3tVIIf27pBy43+GGh/cg+1aBVHPFOk= X-Received: by 2002:a37:5541:: with SMTP id j62mr992115qkb.180.1641845068941; Mon, 10 Jan 2022 12:04:28 -0800 (PST) MIME-Version: 1.0 Date: Mon, 10 Jan 2022 21:04:17 +0100 Message-ID: Subject: [PATCH] i386: Introduce V2QImode vector compares [PR103861] To: "gcc-patches@gcc.gnu.org" X-Spam-Status: No, score=-9.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Uros Bizjak via Gcc-patches From: Uros Bizjak Reply-To: Uros Bizjak Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Add V2QImode vector compares with SSE registers. 2022-01-10 Uroš Bizjak gcc/ChangeLog: PR target/103861 * config/i386/i386-expand.c (ix86_expand_int_sse_cmp): Handle V2QImode. * config/i386/mmx.md (3): Use VI1_16_32 mode iterator. (*eq3): Ditto. (*gt3): Ditto. (*xop_maskcmp3): Ditto. (*xop_maskcmp_uns3): Ditto. (vec_cmp): Ditto. (vec_cmpu): Ditto. gcc/testsuite/ChangeLog: PR target/103861 * gcc.target/i386/pr103861-2.c: New test. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Pushed to master. Uros. diff --git a/gcc/config/i386/i386-expand.c b/gcc/config/i386/i386-expand.c index 95bba254daf..add748bcf40 100644 --- a/gcc/config/i386/i386-expand.c +++ b/gcc/config/i386/i386-expand.c @@ -4444,6 +4444,12 @@ ix86_expand_int_sse_cmp (rtx dest, enum rtx_code code, rtx cop0, rtx cop1, else if (code == GT && TARGET_SSE4_1) gen = gen_sminv4qi3; break; + case E_V2QImode: + if (code == GTU && TARGET_SSE2) + gen = gen_uminv2qi3; + else if (code == GT && TARGET_SSE4_1) + gen = gen_sminv2qi3; + break; case E_V8HImode: if (code == GTU && TARGET_SSE4_1) gen = gen_uminv8hi3; @@ -4537,6 +4543,7 @@ ix86_expand_int_sse_cmp (rtx dest, enum rtx_code code, rtx cop0, rtx cop1, case E_V16QImode: case E_V8QImode: case E_V4QImode: + case E_V2QImode: case E_V8HImode: case E_V4HImode: case E_V2HImode: diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 4fc3e00f100..91d642187be 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -1824,10 +1824,10 @@ (set_attr "mode" "DI,TI,TI")]) (define_insn "*3" - [(set (match_operand:VI_32 0 "register_operand" "=x,Yw") - (sat_plusminus:VI_32 - (match_operand:VI_32 1 "register_operand" "0,Yw") - (match_operand:VI_32 2 "register_operand" "x,Yw")))] + [(set (match_operand:VI_16_32 0 "register_operand" "=x,Yw") + (sat_plusminus:VI_16_32 + (match_operand:VI_16_32 1 "register_operand" "0,Yw") + (match_operand:VI_16_32 2 "register_operand" "x,Yw")))] "TARGET_SSE2" "@ p\t{%2, %0|%0, %2} @@ -2418,10 +2418,10 @@ (set_attr "mode" "DI,TI,TI")]) (define_insn "*eq3" - [(set (match_operand:VI_32 0 "register_operand" "=x,x") - (eq:VI_32 - (match_operand:VI_32 1 "register_operand" "%0,x") - (match_operand:VI_32 2 "register_operand" "x,x")))] + [(set (match_operand:VI_16_32 0 "register_operand" "=x,x") + (eq:VI_16_32 + (match_operand:VI_16_32 1 "register_operand" "%0,x") + (match_operand:VI_16_32 2 "register_operand" "x,x")))] "TARGET_SSE2" "@ pcmpeq\t{%2, %0|%0, %2} @@ -2446,10 +2446,10 @@ (set_attr "mode" "DI,TI,TI")]) (define_insn "*gt3" - [(set (match_operand:VI_32 0 "register_operand" "=x,x") - (gt:VI_32 - (match_operand:VI_32 1 "register_operand" "0,x") - (match_operand:VI_32 2 "register_operand" "x,x")))] + [(set (match_operand:VI_16_32 0 "register_operand" "=x,x") + (gt:VI_16_32 + (match_operand:VI_16_32 1 "register_operand" "0,x") + (match_operand:VI_16_32 2 "register_operand" "x,x")))] "TARGET_SSE2" "@ pcmpgt\t{%2, %0|%0, %2} @@ -2473,10 +2473,10 @@ (set_attr "mode" "TI")]) (define_insn "*xop_maskcmp3" - [(set (match_operand:VI_32 0 "register_operand" "=x") - (match_operator:VI_32 1 "ix86_comparison_int_operator" - [(match_operand:VI_32 2 "register_operand" "x") - (match_operand:VI_32 3 "register_operand" "x")]))] + [(set (match_operand:VI_16_32 0 "register_operand" "=x") + (match_operator:VI_16_32 1 "ix86_comparison_int_operator" + [(match_operand:VI_16_32 2 "register_operand" "x") + (match_operand:VI_16_32 3 "register_operand" "x")]))] "TARGET_XOP" "vpcom%Y1\t{%3, %2, %0|%0, %2, %3}" [(set_attr "type" "sse4arg") @@ -2501,10 +2501,10 @@ (set_attr "mode" "TI")]) (define_insn "*xop_maskcmp_uns3" - [(set (match_operand:VI_32 0 "register_operand" "=x") - (match_operator:VI_32 1 "ix86_comparison_uns_operator" - [(match_operand:VI_32 2 "register_operand" "x") - (match_operand:VI_32 3 "register_operand" "x")]))] + [(set (match_operand:VI_16_32 0 "register_operand" "=x") + (match_operator:VI_16_32 1 "ix86_comparison_uns_operator" + [(match_operand:VI_16_32 2 "register_operand" "x") + (match_operand:VI_16_32 3 "register_operand" "x")]))] "TARGET_XOP" "vpcom%Y1u\t{%3, %2, %0|%0, %2, %3}" [(set_attr "type" "ssecmp") @@ -2527,10 +2527,10 @@ }) (define_expand "vec_cmp" - [(set (match_operand:VI_32 0 "register_operand") - (match_operator:VI_32 1 "" - [(match_operand:VI_32 2 "register_operand") - (match_operand:VI_32 3 "register_operand")]))] + [(set (match_operand:VI_16_32 0 "register_operand") + (match_operator:VI_16_32 1 "" + [(match_operand:VI_16_32 2 "register_operand") + (match_operand:VI_16_32 3 "register_operand")]))] "TARGET_SSE2" { bool ok = ix86_expand_int_vec_cmp (operands); @@ -2551,10 +2551,10 @@ }) (define_expand "vec_cmpu" - [(set (match_operand:VI_32 0 "register_operand") - (match_operator:VI_32 1 "" - [(match_operand:VI_32 2 "register_operand") - (match_operand:VI_32 3 "register_operand")]))] + [(set (match_operand:VI_16_32 0 "register_operand") + (match_operator:VI_16_32 1 "" + [(match_operand:VI_16_32 2 "register_operand") + (match_operand:VI_16_32 3 "register_operand")]))] "TARGET_SSE2" { bool ok = ix86_expand_int_vec_cmp (operands); diff --git a/gcc/testsuite/gcc.target/i386/pr103861-2.c b/gcc/testsuite/gcc.target/i386/pr103861-2.c new file mode 100644 index 00000000000..471f50ca09f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr103861-2.c @@ -0,0 +1,21 @@ +/* PR target/103861 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2" } */ + +typedef char vec __attribute__((vector_size(2))); + +vec lt (vec a, vec b) { return a < b; } +vec le (vec a, vec b) { return a <= b; } +vec eq (vec a, vec b) { return a == b; } +vec ne (vec a, vec b) { return a != b; } +vec ge (vec a, vec b) { return a >= b; } +vec gt (vec a, vec b) { return a > b; } + +typedef unsigned char uvec __attribute__((vector_size(2))); + +vec ltu (uvec a, uvec b) { return a < b; } +vec leu (uvec a, uvec b) { return a <= b; } +vec geu (uvec a, uvec b) { return a >= b; } +vec gtu (uvec a, uvec b) { return a > b; } + +/* { dg-final { scan-assembler-not "cmpb" } } */