From patchwork Thu Sep 1 18:22:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 57253 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 5F83C38582AF for ; Thu, 1 Sep 2022 18:23:08 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 5F83C38582AF DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1662056588; bh=9O0W4z+DVN0JItBj7Bd3mm5PyDludG5n4+5EqeYpP7Q=; h=Date:Subject:To:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=G3s0m9yzjKHPQ/yKrPW2eLCzafmdGaWRWvGKzj0uQBiGdlIOPjXdf/AfuOlyR5tvt xh5/95unHnyB00RxsE3kE+fvoopP+hl0lb6WnK7gYe3xg+eNRACIJzp/69KIrUzPvX NgKadTPlHvy7DJiFmcINkQf0lReyo9jMHQsd8rK8= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-qt1-x82d.google.com (mail-qt1-x82d.google.com [IPv6:2607:f8b0:4864:20::82d]) by sourceware.org (Postfix) with ESMTPS id 9665C3858C52 for ; Thu, 1 Sep 2022 18:22:38 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 9665C3858C52 Received: by mail-qt1-x82d.google.com with SMTP id r6so14120481qtx.6 for ; Thu, 01 Sep 2022 11:22:38 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=to:subject:message-id:date:from:mime-version:x-gm-message-state :from:to:cc:subject:date; bh=9O0W4z+DVN0JItBj7Bd3mm5PyDludG5n4+5EqeYpP7Q=; b=IO/OUAd8MjHOUTLE8TqVOCCdIq2sLJejSnsKEN/CA427W9yOhXak48VWTh8GqzVZf3 qsz3MjO0xbYhkzGBYUysFPRsEyzWcTEWwUHsSKFM2sS8n9V88eOgWHqJ1mnhuUnhdg+r Jy6RDWxPkicu5oq/FDZ+kdYKWrP8YiZd6LSzpAwZVdKjESy/1EM+z12yWRj4ZaFKNqPh Ki8upeGqEA4HdrflWLUhkkt1BV/GUX16E0tT1NEwvuy7uhubxerhP/EsDsIlZ54ZeAVM mVHaR8Unn9Uhgg5EQeZJmKvW7nR7+S9JII4xEquvoqt3LyZ0KiLonJxO1kZraHNkX4hw fVdw== X-Gm-Message-State: ACgBeo1QVSKfyec6mKQN0V9XB64rn52YWDl7CEkHaZNEBGxI6FAL2xTi aRki+ThQFPTOF6usjkMpIO9ES2Sxo0aiGRivlp9uF+HRFzw= X-Google-Smtp-Source: AA6agR6KYLJZ5mb/N7LJ3sAabczqa6bWzonHNZQFiLqH522ac897Nzgvn3zm01zpoKyXccIKXuvG5QQRsaH+ricQAfs= X-Received: by 2002:a05:622a:205:b0:343:282:3d0e with SMTP id b5-20020a05622a020500b0034302823d0emr24959653qtx.436.1662056557731; Thu, 01 Sep 2022 11:22:37 -0700 (PDT) MIME-Version: 1.0 Date: Thu, 1 Sep 2022 20:22:26 +0200 Message-ID: Subject: [PATCH] i386: Fix conversion of move to/from AX_REG into xchg [PR106707] To: "gcc-patches@gcc.gnu.org" X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_SHORT, LIKELY_SPAM_BODY, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Uros Bizjak via Gcc-patches From: Uros Bizjak Reply-To: Uros Bizjak Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" The conversion of a move pattern where both operands are AX_REG should be prevented. 2022-09-01 Uroš Bizjak gcc/ChangeLog: PR target/106707 * config/i386/i386.md (moves to/from AX_REG into xchg peephole2): Do not convert a move pattern where both operands are AX_REG. gcc/testsuite/ChangeLog: PR target/106707 * gcc.target/i386/pr106707.c: New test. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Pushed to master. Uros. diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index a4a18cf89f5..1aef1af594d 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -3043,8 +3043,8 @@ (define_peephole2 [(set (match_operand:SWI48 0 "general_reg_operand") (match_operand:SWI48 1 "general_reg_operand"))] "optimize_size > 1 - && (REGNO (operands[0]) == AX_REG - || REGNO (operands[1]) == AX_REG) + && ((REGNO (operands[0]) == AX_REG) + != (REGNO (operands[1]) == AX_REG)) && optimize_insn_for_size_p () && peep2_reg_dead_p (1, operands[1])" [(parallel [(set (match_dup 0) (match_dup 1)) diff --git a/gcc/testsuite/gcc.target/i386/pr106707.c b/gcc/testsuite/gcc.target/i386/pr106707.c new file mode 100644 index 00000000000..a127ccd4679 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr106707.c @@ -0,0 +1,19 @@ +/* PR target/106707 */ +/* { dg-do compile { target int128 } } */ +/* { dg-options "-Oz -g -fno-cprop-registers -fno-dce" } */ + +typedef unsigned __attribute__((__vector_size__ (8))) V; + +unsigned __int128 ii; +unsigned x, y; + +V v; + +void +foo (long a) +{ + long l = a != x; + int i = __builtin_add_overflow_p (y * ii, 0, 0); + V u = ii < x | v, w = x <= u < i & y <= x / ii; + v = __builtin_shufflevector (v, w, 1, 2) + (V) l; +}