From patchwork Fri Jun 17 15:22:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 55172 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id DEFF4386CE5C for ; Fri, 17 Jun 2022 15:23:04 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org DEFF4386CE5C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1655479384; bh=gA27JTcxcl8/NUA1m69fz5TA1Wdy/ZeoFHYev6BpP7U=; h=Date:Subject:To:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=Q8s4IjEN6n3eEZy93KCi5Ot9VTkqravwto0js/O1WQQUq03Up6sOeSHDhM8xz1F+O utTx98YRRNSg16n2bAqH9dPvqLypFGuMumVAOBK3YjfJgxvJsJB3upmA5o1WKJJOnz 6UDixv7vd/8MOY0jOHv2dKDkknR/IlYKFCHvmfsw= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-qk1-x72f.google.com (mail-qk1-x72f.google.com [IPv6:2607:f8b0:4864:20::72f]) by sourceware.org (Postfix) with ESMTPS id 5441E3857427 for ; Fri, 17 Jun 2022 15:22:34 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 5441E3857427 Received: by mail-qk1-x72f.google.com with SMTP id l192so3357329qke.13 for ; Fri, 17 Jun 2022 08:22:34 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:from:date:message-id:subject:to; bh=gA27JTcxcl8/NUA1m69fz5TA1Wdy/ZeoFHYev6BpP7U=; b=RhPD5O+sJxgwEjuwzB6tEVpKcA9eK9aP+ToUORLdUCEn9REzj4SF/yLTHaMv4f5oiV hHQoLanpli/EpDfjFOALGEFZwCjlBiN2ybdpW+knvJ9CiGba0Gt+OCXszz+nXgANRMD7 bXPwSjPCeoeshgSOYCUVrkYZ/IjYsuP70s/57VMIjayqFH7JJpqpdN1GUa8HloQ+3wIk ZZyRKSBX104MywozEF9sWjFC4+HbgKBzOt+U/DBggI1XfazOINNxIoo+WzBWHg1CCkwV pJ+qOoxbUpbjQWV5PbcUUlMFlzJWpENNBqHzCUWQd/awCNsZGGS+KJfGO5Kvi+DmAM+9 ZJsw== X-Gm-Message-State: AJIora/sCIb2DOqJ2paq1FTTtyNdxuKAeKbTVhYruDK6N8pJ6om7urFq +UePYR18UdlBPbUVwCzr+JReSdW8bslicNXTdiX4KEcKs96XoQ== X-Google-Smtp-Source: AGRyM1tRfO70KruCeCfDrQqWLmUkow+R/FsrxbtiYA84a0+PDLSj4KNHQspGorPqxtejtBCdeMgqPyWdFnocS6SUARA= X-Received: by 2002:a05:620a:1a0d:b0:6a6:ba92:d82b with SMTP id bk13-20020a05620a1a0d00b006a6ba92d82bmr7439919qkb.522.1655479353470; Fri, 17 Jun 2022 08:22:33 -0700 (PDT) MIME-Version: 1.0 Date: Fri, 17 Jun 2022 17:22:22 +0200 Message-ID: Subject: [PATCH] alpha: Introduce target specific store_data_bypass_p function [PR105209] To: "gcc-patches@gcc.gnu.org" X-Spam-Status: No, score=-8.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Uros Bizjak via Gcc-patches From: Uros Bizjak Reply-To: Uros Bizjak Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" This patch introduces alpha-specific version of store_data_bypass_p that ignores TRAP_IF that would result in assertion failure (and internal compiler error) in the generic store_data_bypass_p function. While at it, also remove ev4_ist_c reservation, store_data_bypass_p can handle the patterns with multiple sets since some time ago. 2022-06-17 Uroš Bizjak gcc/ChangeLog: PR target/105209 * config/alpha/alpha-protos.h (alpha_store_data_bypass_p): New. * config/alpha/alpha.cc (alpha_store_data_bypass_p): New function. (alpha_store_data_bypass_p_1): Ditto. * config/alpha/ev4.md: Use alpha_store_data_bypass_p instead of generic store_data_bypass_p. (ev4_ist_c): Remove insn reservation. gcc/testsuite/ChangeLog: PR target/105209 * gcc.target/alpha/pr105209.c: New test. Tested with a cross-compiler. Pushed to master. Uros. diff --git a/gcc/config/alpha/alpha-protos.h b/gcc/config/alpha/alpha-protos.h index 0c832bf039c..adfdd774ef4 100644 --- a/gcc/config/alpha/alpha-protos.h +++ b/gcc/config/alpha/alpha-protos.h @@ -73,6 +73,8 @@ extern void alpha_end_function (FILE *, const char *, tree); extern bool alpha_find_lo_sum_using_gp (rtx); +extern int alpha_store_data_bypass_p (rtx_insn *, rtx_insn *); + #ifdef REAL_VALUE_TYPE extern int check_float_value (machine_mode, REAL_VALUE_TYPE *, int); #endif diff --git a/gcc/config/alpha/alpha.cc b/gcc/config/alpha/alpha.cc index 3db53374c9e..0a85e66fa89 100644 --- a/gcc/config/alpha/alpha.cc +++ b/gcc/config/alpha/alpha.cc @@ -7564,6 +7564,75 @@ alpha_does_function_need_gp (void) return 0; } +/* Helper function for alpha_store_data_bypass_p, handle just a single SET + IN_SET. */ + +static bool +alpha_store_data_bypass_p_1 (rtx_insn *out_insn, rtx in_set) +{ + if (!MEM_P (SET_DEST (in_set))) + return false; + + rtx out_set = single_set (out_insn); + if (out_set) + return !reg_mentioned_p (SET_DEST (out_set), SET_DEST (in_set)); + + rtx out_pat = PATTERN (out_insn); + if (GET_CODE (out_pat) != PARALLEL) + return false; + + for (int i = 0; i < XVECLEN (out_pat, 0); i++) + { + rtx out_exp = XVECEXP (out_pat, 0, i); + + if (GET_CODE (out_exp) == CLOBBER || GET_CODE (out_exp) == USE + || GET_CODE (out_exp) == TRAP_IF) + continue; + + gcc_assert (GET_CODE (out_exp) == SET); + + if (reg_mentioned_p (SET_DEST (out_exp), SET_DEST (in_set))) + return false; + } + + return true; +} + +/* True if the dependency between OUT_INSN and IN_INSN is on the store + data not the address operand(s) of the store. IN_INSN and OUT_INSN + must be either a single_set or a PARALLEL with SETs inside. + + This alpha-specific version of store_data_bypass_p ignores TRAP_IF + that would result in assertion failure (and internal compiler error) + in the generic store_data_bypass_p function. */ + +int +alpha_store_data_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn) +{ + rtx in_set = single_set (in_insn); + if (in_set) + return alpha_store_data_bypass_p_1 (out_insn, in_set); + + rtx in_pat = PATTERN (in_insn); + if (GET_CODE (in_pat) != PARALLEL) + return false; + + for (int i = 0; i < XVECLEN (in_pat, 0); i++) + { + rtx in_exp = XVECEXP (in_pat, 0, i); + + if (GET_CODE (in_exp) == CLOBBER || GET_CODE (in_exp) == USE + || GET_CODE (in_exp) == TRAP_IF) + continue; + + gcc_assert (GET_CODE (in_exp) == SET); + + if (!alpha_store_data_bypass_p_1 (out_insn, in_exp)) + return false; + } + + return true; +} /* Helper function to set RTX_FRAME_RELATED_P on instructions, including sequences. */ diff --git a/gcc/config/alpha/ev4.md b/gcc/config/alpha/ev4.md index 01b9a727a18..c8ff4ed8f0d 100644 --- a/gcc/config/alpha/ev4.md +++ b/gcc/config/alpha/ev4.md @@ -44,14 +44,7 @@ (define_insn_reservation "ev4_ld" 1 ; Stores can issue before the data (but not address) is ready. (define_insn_reservation "ev4_ist" 1 (and (eq_attr "tune" "ev4") - (eq_attr "type" "ist")) - "ev4_ib1+ev4_abox") - -; ??? Separate from ev4_ist because store_data_bypass_p can't handle -; the patterns with multiple sets, like store-conditional. -(define_insn_reservation "ev4_ist_c" 1 - (and (eq_attr "tune" "ev4") - (eq_attr "type" "st_c")) + (eq_attr "type" "ist,st_c")) "ev4_ib1+ev4_abox") (define_insn_reservation "ev4_fst" 1 @@ -110,7 +103,7 @@ (define_bypass 1 "ev4_icmp" "ev4_ibr") (define_bypass 0 "ev4_iaddlog,ev4_shiftcm,ev4_icmp" "ev4_ist" - "store_data_bypass_p") + "alpha_store_data_bypass_p") ; Multiplies use a non-pipelined imul unit. Also, "no [ebox] insn can ; be issued exactly three cycles before an integer multiply completes". @@ -121,7 +114,7 @@ (define_insn_reservation "ev4_imulsi" 21 (eq_attr "opsize" "si"))) "ev4_ib0+ev4_imul,ev4_imul*18,ev4_ebox") -(define_bypass 20 "ev4_imulsi" "ev4_ist" "store_data_bypass_p") +(define_bypass 20 "ev4_imulsi" "ev4_ist" "alpha_store_data_bypass_p") (define_insn_reservation "ev4_imuldi" 23 (and (eq_attr "tune" "ev4") @@ -129,7 +122,7 @@ (define_insn_reservation "ev4_imuldi" 23 (eq_attr "opsize" "!si"))) "ev4_ib0+ev4_imul,ev4_imul*20,ev4_ebox") -(define_bypass 22 "ev4_imuldi" "ev4_ist" "store_data_bypass_p") +(define_bypass 22 "ev4_imuldi" "ev4_ist" "alpha_store_data_bypass_p") ; Most FP insns have a 6 cycle latency, but with a 4 cycle bypass back in. (define_insn_reservation "ev4_fpop" 6 diff --git a/gcc/testsuite/gcc.target/alpha/pr105209.c b/gcc/testsuite/gcc.target/alpha/pr105209.c new file mode 100644 index 00000000000..b89be96dc1d --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/pr105209.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftrapv -mcpu=ev4" } */ + +typedef struct tnode_t { + struct tnode_t *tn_left, *tn_right; + int v_quad; +} tnode_t; + +int constant_addr(const tnode_t *, long *); +int constant_addr(const tnode_t *tn, long *offsp) +{ + long offs1 = 0, offs2 = 0; + + if (tn->v_quad > 0) { + offs1 = tn->v_quad; + return 0; + } else if (tn->v_quad > -1) { + offs2 = tn->tn_right->v_quad; + if (!constant_addr(tn->tn_left, &offs1)) + return 0; + } else { + return 0; + } + *offsp = offs1 + offs2; + return 1; +}