From patchwork Fri Dec 17 10:04:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prathamesh Kulkarni X-Patchwork-Id: 49045 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 52A9B3858016 for ; Fri, 17 Dec 2021 10:06:08 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 52A9B3858016 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1639735568; bh=jkcLPMQCdSVeRrhWc9tOt7p9pwvt+qoSO5I+Pv5Zi7k=; h=Date:Subject:To:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=ncSsoAL79SLKsFfkd+rqDLpggjffYtD2eajfVT+oil0Q8g4RiAPzM9FOQ1P2X213H SCkfXT9FY1zJx/TGgqxvbKWIzgPAJVPRkMvk6zWGw+Xx29SrgtnIDN9gCCc/uVAZol SVIzn78geKiB9eVKFmv7MCsRVtEJIIAfLb856mH8= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-wr1-x429.google.com (mail-wr1-x429.google.com [IPv6:2a00:1450:4864:20::429]) by sourceware.org (Postfix) with ESMTPS id 63B6E3858017 for ; Fri, 17 Dec 2021 10:04:39 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 63B6E3858017 Received: by mail-wr1-x429.google.com with SMTP id v11so2963317wrw.10 for ; Fri, 17 Dec 2021 02:04:39 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:from:date:message-id:subject:to; bh=jkcLPMQCdSVeRrhWc9tOt7p9pwvt+qoSO5I+Pv5Zi7k=; b=ZtCZbXvQ/H4z8Bdxa9qW92moKWW0fuUMwrS88obUEnXWmAwbg7qXHcE35wEkXolSgM oY0KlGdYR6Mub3Ytb8uIVemfYQT6UETIhncj+S0+Yg22V47BsnPUcV5YE+3EvPLdtRQs an+utIZ7X1BGbnGxpS9gwyEl8zdq9tDyJUQQq7KUVK5kPMoFmVhHJS+/zuIHP0+TTdKu AIlKPDE0M2+FueDR8O/l6PepdFCY5rktklOC4yEke4GEfQFJAXCX0ggqyxTcwYn0Vefn 0T8OYoJk9ITyMwo0kUarplu3jCMwQuqYyRfUlku7zj8RYP9qKzt+AZ18fmJTkhDhdY5m 0W9A== X-Gm-Message-State: AOAM531HBmsIQuCpYkcDdgDlbr2Kl1Ocaglz7NkrN/WDY743BdHwnLhB 4T7q+hJygixLAbbI1S00odRdMmsh+R6xeYlfBBEc8Ss14h4= X-Google-Smtp-Source: ABdhPJy1gQOr7JrRlxZe1ce4Fz48d9bzJKjqZHU7G+wND1K47RiKaEUG5uLlT+sGKG19mI4Z82QTwXy6lLbq6YUCwKk= X-Received: by 2002:a5d:4706:: with SMTP id y6mr1892089wrq.435.1639735478049; Fri, 17 Dec 2021 02:04:38 -0800 (PST) MIME-Version: 1.0 Date: Fri, 17 Dec 2021 15:34:01 +0530 Message-ID: Subject: [1/2] PR96463 - aarch64 specific changes To: gcc Patches , Richard Sandiford X-Spam-Status: No, score=-9.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Prathamesh Kulkarni via Gcc-patches From: Prathamesh Kulkarni Reply-To: Prathamesh Kulkarni Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Hi, The patch folds: lhs = svld1rq ({-1, -1, -1, ...}, &v[0]) into: lhs = vec_perm_expr and expands above vec_perm_expr using aarch64_expand_sve_dupq. With patch, for following test: #include #include svint32_t foo (int32x4_t x) { return svld1rq (svptrue_b8 (), &x[0]); } it generates following code: foo: .LFB4350: dup z0.q, z0.q[0] ret and passes bootstrap+test on aarch64-linux-gnu. But I am not sure if the changes to aarch64_evpc_sve_tbl are correct. Thanks, Prathamesh diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc index 02e42a71e5e..e21bbec360c 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc +++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc @@ -1207,6 +1207,56 @@ public: insn_code icode = code_for_aarch64_sve_ld1rq (e.vector_mode (0)); return e.use_contiguous_load_insn (icode); } + + gimple * + fold (gimple_folder &f) const OVERRIDE + { + tree arg0 = gimple_call_arg (f.call, 0); + tree arg1 = gimple_call_arg (f.call, 1); + + /* Transform: + lhs = svld1rq ({-1, -1, ... }, &v[0]) + into: + lhs = vec_perm_expr. + on little endian target. */ + + if (!BYTES_BIG_ENDIAN + && integer_all_onesp (arg0) + && TREE_CODE (arg1) == ADDR_EXPR) + { + tree t = TREE_OPERAND (arg1, 0); + if (TREE_CODE (t) == ARRAY_REF) + { + tree index = TREE_OPERAND (t, 1); + t = TREE_OPERAND (t, 0); + if (integer_zerop (index) && TREE_CODE (t) == VIEW_CONVERT_EXPR) + { + t = TREE_OPERAND (t, 0); + tree vectype = TREE_TYPE (t); + if (VECTOR_TYPE_P (vectype) + && known_eq (TYPE_VECTOR_SUBPARTS (vectype), 4u) + && wi::to_wide (TYPE_SIZE (vectype)) == 128) + { + tree lhs = gimple_call_lhs (f.call); + tree lhs_type = TREE_TYPE (lhs); + int source_nelts = TYPE_VECTOR_SUBPARTS (vectype).to_constant (); + vec_perm_builder sel (TYPE_VECTOR_SUBPARTS (lhs_type), source_nelts, 1); + for (int i = 0; i < source_nelts; i++) + sel.quick_push (i); + + vec_perm_indices indices (sel, 1, source_nelts); + if (!can_vec_perm_const_p (TYPE_MODE (lhs_type), indices)) + return NULL; + + tree mask = vec_perm_indices_to_tree (lhs_type, indices); + return gimple_build_assign (lhs, VEC_PERM_EXPR, t, t, mask); + } + } + } + } + + return NULL; + } }; class svld1ro_impl : public load_replicate diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index f07330cff4f..af27f550be3 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -23002,8 +23002,32 @@ aarch64_evpc_sve_tbl (struct expand_vec_perm_d *d) machine_mode sel_mode = related_int_vector_mode (d->vmode).require (); rtx sel = vec_perm_indices_to_rtx (sel_mode, d->perm); + if (d->one_vector_p) - emit_unspec2 (d->target, UNSPEC_TBL, d->op0, force_reg (sel_mode, sel)); + { + bool use_dupq = false; + /* Check if sel is dup vector with encoded elements {0, 1, 2, ... nelts} */ + if (GET_CODE (sel) == CONST_VECTOR + && !GET_MODE_NUNITS (GET_MODE (sel)).is_constant () + && CONST_VECTOR_DUPLICATE_P (sel)) + { + unsigned nelts = const_vector_encoded_nelts (sel); + unsigned i; + for (i = 0; i < nelts; i++) + { + rtx elem = CONST_VECTOR_ENCODED_ELT(sel, i); + if (!(CONST_INT_P (elem) && INTVAL(elem) == i)) + break; + } + if (i == nelts) + use_dupq = true; + } + + if (use_dupq) + aarch64_expand_sve_dupq (d->target, GET_MODE (d->target), d->op0); + else + emit_unspec2 (d->target, UNSPEC_TBL, d->op0, force_reg (sel_mode, sel)); + } else aarch64_expand_sve_vec_perm (d->target, d->op0, d->op1, sel); return true;