From patchwork Tue Jan 17 10:46:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prathamesh Kulkarni X-Patchwork-Id: 63266 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 6B10D3858414 for ; Tue, 17 Jan 2023 10:47:54 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 6B10D3858414 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1673952474; bh=qHeH+uVippo1j8HU9T24lJsQ9IX8V25APCSU9PktxkE=; h=Date:Subject:To:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=BgFLQQEJwteswTyaEz7LMYxmCl4IfYSJ7CxOldCd+P/CXlkY7o/xgb/v/DV+yGmkS xkBPBiQVYdSI+Z52ySvS5nXBaeoraQKr6Hxu5w5GPKFJHgiGhLa5L6Zfkm7L4ta1Zb fgqYOwbj3WJJPN4rxFIR0Ka0l3Z6UbZzHJSnoxGQ= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-wm1-x332.google.com (mail-wm1-x332.google.com [IPv6:2a00:1450:4864:20::332]) by sourceware.org (Postfix) with ESMTPS id D902E3858414 for ; Tue, 17 Jan 2023 10:47:24 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D902E3858414 Received: by mail-wm1-x332.google.com with SMTP id j34-20020a05600c1c2200b003da1b054057so9758766wms.5 for ; Tue, 17 Jan 2023 02:47:24 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=to:subject:message-id:date:from:mime-version:x-gm-message-state :from:to:cc:subject:date:message-id:reply-to; bh=qHeH+uVippo1j8HU9T24lJsQ9IX8V25APCSU9PktxkE=; b=KqYRojMNB2Sr1cJ37qMr0rhb+LZT83w862+KTF9AzZI7On3Fuk7BJpOk83EObXRNyx NKabu9jqCldXNPWNOK1XFDKd4ziQvE385Uuouzj87TohkeG3RdCGfD1DJAwG7i88H1je Dqhc9k6pw9JCLPOxv9B1eSpy6BQADq1ZGmhWf37CIYf3ENCT60UfTVVnsKqU+M0NODbX v6eZ4OWHiRSrWrwPZap1xm/IyzC6ndy8BB942iv5k9R19d0v0Pm+ekUKJUhZE7g0t6lb xnTxy/SM7lBW0Bnt6j7OcOYQllWUlNxQQnkjgk6bqTcXTWuafyV4vrHxIADfaRC8thm6 rg+g== X-Gm-Message-State: AFqh2kqzQw74k2HKItBOC45SyEsRCqKGnaQVdBATJHVogSUR1QoV2qS9 i5tk2Dc63g7T5wTS0Ebv55gE/RxZ/cnvJqV4IK8Nyy2nv55RxA== X-Google-Smtp-Source: AMrXdXsxNU8DroIV6hdiATdz2ApcAMy1azPA+uolc5oHU3WV3lIgp26RqflDqAenhZdz2GHSIf4QBg0ECZfrdMsDUPs= X-Received: by 2002:a05:600c:354d:b0:3da:f794:0 with SMTP id i13-20020a05600c354d00b003daf7940000mr119153wmq.147.1673952443161; Tue, 17 Jan 2023 02:47:23 -0800 (PST) MIME-Version: 1.0 Date: Tue, 17 Jan 2023 16:16:45 +0530 Message-ID: Subject: [aarch64] Use wzr/xzr for assigning vector element to 0 To: gcc Patches , Richard Sandiford X-Spam-Status: No, score=-9.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_NUMSUBJECT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Prathamesh Kulkarni via Gcc-patches From: Prathamesh Kulkarni Reply-To: Prathamesh Kulkarni Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Hi Richard, For the following (contrived) test: void foo(int32x4_t v) { v[3] = 0; return v; } -O2 code-gen: foo: fmov s1, wzr ins v0.s[3], v1.s[0] ret I suppose we can instead emit the following code-gen ? foo: ins v0.s[3], wzr ret combine produces: Failed to match this instruction: (set (reg:V4SI 95 [ v ]) (vec_merge:V4SI (const_vector:V4SI [ (const_int 0 [0]) repeated x4 ]) (reg:V4SI 97) (const_int 8 [0x8]))) So, I wrote the following pattern to match the above insn: (define_insn "aarch64_simd_vec_set_zero" [(set (match_operand:VALL_F16 0 "register_operand" "=w") (vec_merge:VALL_F16 (match_operand:VALL_F16 1 "const_dup0_operand" "w") (match_operand:VALL_F16 3 "register_operand" "0") (match_operand:SI 2 "immediate_operand" "i")))] "TARGET_SIMD" { int elt = ENDIAN_LANE_N (, exact_log2 (INTVAL (operands[2]))); operands[2] = GEN_INT ((HOST_WIDE_INT) 1 << elt); return "ins\\t%0.[%p2], wzr"; } ) which now matches the above insn produced by combine. However, in reload dump, it creates a new insn for assigning register to (const_vector (const_int 0)), which results in: (insn 19 8 13 2 (set (reg:V4SI 33 v1 [99]) (const_vector:V4SI [ (const_int 0 [0]) repeated x4 ])) "wzr-test.c":8:1 1269 {*aarch64_simd_movv4si} (nil)) (insn 13 19 14 2 (set (reg/i:V4SI 32 v0) (vec_merge:V4SI (reg:V4SI 33 v1 [99]) (reg:V4SI 32 v0 [97]) (const_int 8 [0x8]))) "wzr-test.c":8:1 1808 {aarch64_simd_vec_set_zerov4si} (nil)) and eventually the code-gen: foo: movi v1.4s, 0 ins v0.s[3], wzr ret To get rid of redundant assignment of 0 to v1, I tried to split the above pattern as in the attached patch. This works to emit code-gen: foo: ins v0.s[3], wzr ret However, I am not sure if this is the right approach. Could you suggest, if it'd be possible to get rid of UNSPEC_SETZERO in the patch ? Thanks, Prathamesh diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 104088f67d2..5130f46c0da 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -1083,6 +1083,39 @@ [(set_attr "type" "neon_ins, neon_from_gp, neon_load1_one_lane")] ) +(define_insn "aarch64_simd_set_zero" + [(set (match_operand:VALL_F16 0 "register_operand" "=w") + (unspec:VALL_F16 [(match_operand:VALL_F16 1 "register_operand" "0") + (match_operand:SI 2 "immediate_operand" "i")] + UNSPEC_SETZERO))] + "TARGET_SIMD" + { + if (GET_MODE_INNER (mode) == DImode) + return "ins\\t%0.[%p2], xzr"; + return "ins\\t%0.[%p2], wzr"; + } + [(set_attr "type" "neon_ins")] +) + +(define_insn_and_split "aarch64_simd_vec_set_zero" + [(set (match_operand:VALL_F16 0 "register_operand" "=w") + (vec_merge:VALL_F16 + (match_operand:VALL_F16 1 "const_dup0_operand" "w") + (match_operand:VALL_F16 3 "register_operand" "0") + (match_operand:SI 2 "immediate_operand" "i")))] + "TARGET_SIMD" + "#" + "&& 1" + [(const_int 0)] + { + int elt = ENDIAN_LANE_N (, exact_log2 (INTVAL (operands[2]))); + operands[2] = GEN_INT ((HOST_WIDE_INT) 1 << elt); + emit_insn (gen_aarch64_simd_set_zero (operands[0], operands[3], operands[2])); + DONE; + } + [(set_attr "type" "neon_ins")] +) + (define_insn "@aarch64_simd_vec_copy_lane" [(set (match_operand:VALL_F16 0 "register_operand" "=w") (vec_merge:VALL_F16 diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 5b26443e5b6..8064841ebb4 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -839,6 +839,7 @@ UNSPEC_FCMUL_CONJ ; Used in aarch64-simd.md. UNSPEC_FCMLA_CONJ ; Used in aarch64-simd.md. UNSPEC_FCMLA180_CONJ ; Used in aarch64-simd.md. + UNSPEC_SETZERO ; Used in aarch64-simd.md. UNSPEC_ASRD ; Used in aarch64-sve.md. UNSPEC_ADCLB ; Used in aarch64-sve2.md. UNSPEC_ADCLT ; Used in aarch64-sve2.md. diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md index ff7f73d3f30..901fa1bd7f9 100644 --- a/gcc/config/aarch64/predicates.md +++ b/gcc/config/aarch64/predicates.md @@ -49,6 +49,13 @@ return CONST_INT_P (op) && IN_RANGE (INTVAL (op), 1, 3); }) +(define_predicate "const_dup0_operand" + (match_code "const_vector") +{ + op = unwrap_const_vec_duplicate (op); + return CONST_INT_P (op) && rtx_equal_p (op, const0_rtx); +}) + (define_predicate "subreg_lowpart_operator" (ior (match_code "truncate") (and (match_code "subreg")