From patchwork Thu Mar 10 13:45:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Xi Ruoyao X-Patchwork-Id: 51855 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 5A09D3857C6C for ; Thu, 10 Mar 2022 13:48:02 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 5A09D3857C6C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1646920082; bh=Rr9/5GhGld61rDZHkzzmVS5qlrPSZFgMy4Yvnof2o5k=; h=Subject:To:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=ahjyJTDsRYf7QQniuLCAXHdsFrVThNxN3MsZIBfbLecEKYlRlIA9hBBzywqhjnoT0 vB+4NnCqoqKNlyXqVUTQzfJZWDVMJnVcHwXDrgAaoPD2ed0asnUL/7IQFAIsaNtk/p LHW/MWK+8onNuP/AqutSXQAy8LEan0qv+bHlHZa8= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mengyan1223.wang (mengyan1223.wang [89.208.246.23]) by sourceware.org (Postfix) with ESMTPS id 53F363857831; Thu, 10 Mar 2022 13:45:56 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 53F363857831 Received: from localhost.localdomain (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature ECDSA (P-384) server-digest SHA384) (Client did not present a certificate) (Authenticated sender: xry111@mengyan1223.wang) by mengyan1223.wang (Postfix) with ESMTPSA id 3B7FD66279; Thu, 10 Mar 2022 08:45:53 -0500 (EST) Message-ID: <9ce1e6d7cbe3fabfbda7e2ab95f3a5b91bcf6309.camel@mengyan1223.wang> Subject: [PATCH v2 RFC, resend] mips: add TARGET_ZERO_CALL_USED_REGS hook [PR104817, PR104820] To: Richard Sandiford Date: Thu, 10 Mar 2022 21:45:50 +0800 In-Reply-To: References: <93ab62b2b9473733e5118f4265b61804978adfd7.camel@mengyan1223.wang> <83a60e540b0346e6006007954ce6ec3d83a4fe17.camel@mengyan1223.wang> User-Agent: Evolution 3.42.4 MIME-Version: 1.0 X-Spam-Status: No, score=-3037.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Xi Ruoyao via Gcc-patches From: Xi Ruoyao Reply-To: Xi Ruoyao Cc: Jeff Law , gcc-patches@gcc.gnu.org, YunQiang Su , Jakub Jelinek Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" On Thu, 2022-03-10 at 21:41 +0800, Xi Ruoyao wrote: > Changes from v1: > >  * Added all zeroed registers into the return value of >    TARGET_ZERO_CALL_USED_REGS.  **The question: is this allowed?** >  * Define mips_zero_fcc insn only for ISA_HAS_8CC and mips_isa > >    MIPS_ISA_MIPS4, because MIPS I-IV and MIPSr6 don't support >    "ISA_HAS_8CC && mips_isa > MIPS_ISA_MIPS4". >  * Change mips_zero_fcc to explicit clear all eight registers. >  * Report an error for MIPS I-IV. My mail client somehow mangled the patch. Resending... -- >8 -- This fixes the ICEs using -fzero-call-used-regs=all for MIPS target. OpenSSH-8.9p1 has started to enable this by default, giving us a reason to fix -fzero-call-used-regs for more targets. gcc/ PR target/xxxxxx (WIP) PR target/xxxxxx (Don't push) * config/mips/mips.cc (mips_zero_call_used_regs): New function. (TARGET_ZERO_CALL_USED_REGS): Define. * config/mips/mips.md (FCC{0..9}_REGNUM): New constants. (mips_zero_fcc): New insn. gcc/testsuite * c-c++-common/zero-scratch-regs-8.c: Enable for MIPS. * c-c++-common/zero-scratch-regs-9.c: Likewise. * c-c++-common/zero-scratch-regs-10.c: Likewise. * c-c++-common/zero-scratch-regs-11.c: Likewise. --- gcc/config/mips/mips.cc | 55 +++++++++++++++++++ gcc/config/mips/mips.md | 20 +++++++ .../c-c++-common/zero-scratch-regs-10.c | 2 +- .../c-c++-common/zero-scratch-regs-11.c | 2 +- .../c-c++-common/zero-scratch-regs-8.c | 2 +- .../c-c++-common/zero-scratch-regs-9.c | 2 +- 6 files changed, 79 insertions(+), 4 deletions(-) diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc index 4f9683e8bf4..59eef515826 100644 --- a/gcc/config/mips/mips.cc +++ b/gcc/config/mips/mips.cc @@ -22611,6 +22611,59 @@ mips_asm_file_end (void) if (NEED_INDICATE_EXEC_STACK) file_end_indicate_exec_stack (); } + +static HARD_REG_SET +mips_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs) +{ + HARD_REG_SET zeroed_hardregs; + CLEAR_HARD_REG_SET (zeroed_hardregs); + + if (TEST_HARD_REG_BIT (need_zeroed_hardregs, HI_REGNUM)) + { + /* Clear HI and LO altogether. MIPS target treats HILO as a + double-word register. */ + machine_mode dword_mode = TARGET_64BIT ? TImode : DImode; + rtx hilo = gen_rtx_REG (dword_mode, MD_REG_FIRST); + rtx zero = CONST0_RTX (dword_mode); + emit_move_insn (hilo, zero); + + SET_HARD_REG_BIT (zeroed_hardregs, HI_REGNUM); + SET_HARD_REG_BIT (zeroed_hardregs, LO_REGNUM); + } + + /* MIPS does not have a simple way to clear one bit in FCC. We just + clear FCC with ctc1 and clobber all FCC bits. */ + HARD_REG_SET fcc = reg_class_contents[ST_REGS] & accessible_reg_set; + if (hard_reg_set_intersect_p (need_zeroed_hardregs, fcc)) + { + static bool issued_error = false; + if (mips_isa <= MIPS_ISA_MIPS4) + { + /* We don't have an easy way to clear FCC on MIPS I, II, III, + and IV. */ + if (!issued_error) + sorry ("%qs not supported on this target", + "-fzero-call-used-regs"); + issued_error = true; + + /* Prevent an ICE. */ + need_zeroed_hardregs &= ~fcc; + } + else + { + /* If the target is MIPSr6, we should not reach here. All other + MIPS targets are ISA_HAS_8CC. */ + gcc_assert (ISA_HAS_8CC); + emit_insn (gen_mips_zero_fcc ()); + zeroed_hardregs |= fcc; + } + } + + need_zeroed_hardregs &= ~zeroed_hardregs; + return (zeroed_hardregs | + default_zero_call_used_regs (need_zeroed_hardregs)); +} + /* Initialize the GCC target structure. */ #undef TARGET_ASM_ALIGNED_HI_OP @@ -22919,6 +22972,8 @@ mips_asm_file_end (void) #undef TARGET_ASM_FILE_END #define TARGET_ASM_FILE_END mips_asm_file_end +#undef TARGET_ZERO_CALL_USED_REGS +#define TARGET_ZERO_CALL_USED_REGS mips_zero_call_used_regs struct gcc_target targetm = TARGET_INITIALIZER; diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index e0f0a582732..36d6a43d67f 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -167,6 +167,14 @@ (define_constants (SET_FCSR_REGNUM 4) (PIC_FUNCTION_ADDR_REGNUM 25) (RETURN_ADDR_REGNUM 31) + (FCC0_REGNUM 67) + (FCC1_REGNUM 68) + (FCC2_REGNUM 69) + (FCC3_REGNUM 70) + (FCC4_REGNUM 71) + (FCC5_REGNUM 72) + (FCC6_REGNUM 73) + (FCC7_REGNUM 74) (CPRESTORE_SLOT_REGNUM 76) (GOT_VERSION_REGNUM 79) @@ -7670,6 +7678,18 @@ (define_insn "*mips_set_fcsr" "TARGET_HARD_FLOAT" "ctc1\t%0,$31") +(define_insn "mips_zero_fcc" + [(set (reg:CC FCC0_REGNUM) (const_int 0)) + (set (reg:CC FCC1_REGNUM) (const_int 0)) + (set (reg:CC FCC2_REGNUM) (const_int 0)) + (set (reg:CC FCC3_REGNUM) (const_int 0)) + (set (reg:CC FCC4_REGNUM) (const_int 0)) + (set (reg:CC FCC5_REGNUM) (const_int 0)) + (set (reg:CC FCC6_REGNUM) (const_int 0)) + (set (reg:CC FCC7_REGNUM) (const_int 0))] + "TARGET_HARD_FLOAT && ISA_HAS_8CC && mips_isa > MIPS_ISA_MIPS4" + "ctc1\t$0,$25") + ;; See tls_get_tp_mips16_ for why this form is used. (define_insn "mips_set_fcsr_mips16_" [(unspec_volatile:SI [(match_operand:P 0 "call_insn_operand" "dS") diff --git a/gcc/testsuite/c-c++-common/zero-scratch-regs-10.c b/gcc/testsuite/c-c++-common/zero-scratch-regs-10.c index 96e0b79b328..c23b2ceb391 100644 --- a/gcc/testsuite/c-c++-common/zero-scratch-regs-10.c +++ b/gcc/testsuite/c-c++-common/zero-scratch-regs-10.c @@ -1,5 +1,5 @@ /* { dg-do run } */ -/* { dg-skip-if "not implemented" { ! { i?86*-*-* x86_64*-*-* sparc*-*-* aarch64*-*-* nvptx*-*-* s390*-*-* } } } */ +/* { dg-skip-if "not implemented" { ! { i?86*-*-* x86_64*-*-* sparc*-*-* aarch64*-*-* nvptx*-*-* s390*-*-* mips*-*-* } } } */ /* { dg-options "-O2" } */ #include diff --git a/gcc/testsuite/c-c++-common/zero-scratch-regs-11.c b/gcc/testsuite/c-c++-common/zero-scratch-regs-11.c index 0714f95a04f..f51f5a2161c 100644 --- a/gcc/testsuite/c-c++-common/zero-scratch-regs-11.c +++ b/gcc/testsuite/c-c++-common/zero-scratch-regs-11.c @@ -1,5 +1,5 @@ /* { dg-do run } */ -/* { dg-skip-if "not implemented" { ! { i?86*-*-* x86_64*-*-* sparc*-*-* aarch64*-*-* arm*-*-* nvptx*-*-* s390*-*-* } } } */ +/* { dg-skip-if "not implemented" { ! { i?86*-*-* x86_64*-*-* sparc*-*-* aarch64*-*-* arm*-*-* nvptx*-*-* s390*-*-* mips*-*-* } } } */ /* { dg-options "-O2 -fzero-call-used-regs=all" } */ #include "zero-scratch-regs-10.c" diff --git a/gcc/testsuite/c-c++-common/zero-scratch-regs-8.c b/gcc/testsuite/c-c++-common/zero-scratch-regs-8.c index aceda7e5cb8..3e5e59b3c79 100644 --- a/gcc/testsuite/c-c++-common/zero-scratch-regs-8.c +++ b/gcc/testsuite/c-c++-common/zero-scratch-regs-8.c @@ -1,5 +1,5 @@ /* { dg-do run } */ -/* { dg-skip-if "not implemented" { ! { i?86*-*-* x86_64*-*-* sparc*-*-* aarch64*-*-* arm*-*-* nvptx*-*-* s390*-*-* } } } */ +/* { dg-skip-if "not implemented" { ! { i?86*-*-* x86_64*-*-* sparc*-*-* aarch64*-*-* arm*-*-* nvptx*-*-* s390*-*-* mips*-*-* } } } */ /* { dg-options "-O2 -fzero-call-used-regs=all-arg" } */ #include "zero-scratch-regs-1.c" diff --git a/gcc/testsuite/c-c++-common/zero-scratch-regs-9.c b/gcc/testsuite/c-c++-common/zero-scratch-regs-9.c index f3152a7a732..d88d61accb2 100644 --- a/gcc/testsuite/c-c++-common/zero-scratch-regs-9.c +++ b/gcc/testsuite/c-c++-common/zero-scratch-regs-9.c @@ -1,5 +1,5 @@ /* { dg-do run } */ -/* { dg-skip-if "not implemented" { ! { i?86*-*-* x86_64*-*-* sparc*-*-* aarch64*-*-* arm*-*-* nvptx*-*-* s390*-*-* } } } */ +/* { dg-skip-if "not implemented" { ! { i?86*-*-* x86_64*-*-* sparc*-*-* aarch64*-*-* arm*-*-* nvptx*-*-* s390*-*-* mips*-*-* } } } */ /* { dg-options "-O2 -fzero-call-used-regs=all" } */ #include "zero-scratch-regs-1.c"