From patchwork Sun Apr 16 15:57:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeff Law X-Patchwork-Id: 67793 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 64C473857027 for ; Sun, 16 Apr 2023 15:57:26 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pj1-x1030.google.com (mail-pj1-x1030.google.com [IPv6:2607:f8b0:4864:20::1030]) by sourceware.org (Postfix) with ESMTPS id 5FBA43858CDB for ; Sun, 16 Apr 2023 15:57:10 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 5FBA43858CDB Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=ventanamicro.com Received: by mail-pj1-x1030.google.com with SMTP id hg14-20020a17090b300e00b002471efa7a8fso10040780pjb.0 for ; Sun, 16 Apr 2023 08:57:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1681660628; x=1684252628; h=subject:from:to:content-language:user-agent:mime-version:date :message-id:from:to:cc:subject:date:message-id:reply-to; bh=iAaBx11O9J9CBlxUJaUy8PKr8QeOoteBecAZnpZ1dC0=; b=ODy6zCsCeHsJnTmVbyvgLcKxKLqxD1f747eMGX/aMYrsCcdbAD8UajHgOOVz3zyILa 7FOtiye4KxjlQt8Xr6O7SeXMgqguYNkalZ+90MReRVHRwJzYxY39ygy77LgUYQhPFs5F ZJuZhojk2YZTwQ0Hk9LUorwbWUTT2mom7Jwrx7KWuEcw3kYJApD9PWgP+TVZF1qFu/Oi 6Lpgvzx4UiICnhsWEJyrs7NUZdu1/WQzY975A+Ud/kcK9lQ0P5JdvCZ0laTrR6pxMJvd sBIqZPm8ZVkp6tHD9jL219xVauWdLcAQpggX6MubuLwkVdA9J1gEKM7ikBesmr6nr3SP Cjzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681660628; x=1684252628; h=subject:from:to:content-language:user-agent:mime-version:date :message-id:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=iAaBx11O9J9CBlxUJaUy8PKr8QeOoteBecAZnpZ1dC0=; b=kVfqpHGbIllVDIxAjAPXQvhm6SOwllD9eolnOft0zJwgShhOi5lp+TyExrs5k7lBaz 9FB35mQ/dTyMoIo7JA1kgzGN/wTYDjCZfnHishLs+3WnxPHzc3/d+kIo89mGHs5Z4sWa jqFqjx39hp0qAf48ddDQ1G8IuK40U73Cn9bBfCesYWcx7GhA5flO5aa4zPqhUqCGkpam ZkW/oiktutcXSWmoHj26kJI4TPt0M2Onif4HGcmbKQt0ffvQh3YiY0Ne3e075vseLgxb 7nghvLER6yGn594TvaigjSkCs1m+xUqPPmmBDpUz28GM+X1u5d++/wObyEhQwoaRb4gc l96Q== X-Gm-Message-State: AAQBX9fe7F4lCYwe0/09S+rScDLvj0+C957nLtPgl1uU3DtirkcktT2y SNbaObNFCAU7/xqeLs9Ywp7HUtkM6ZNr6JxuJyk= X-Google-Smtp-Source: AKy350Yx8hfjs48Q0cucVOwHMyuk/VBwgOphmvUFtuzoB3H4zP0dMOMkKviI5EJhAOIYMVvZlnUxGA== X-Received: by 2002:a17:90a:62c1:b0:247:13f5:47de with SMTP id k1-20020a17090a62c100b0024713f547demr11875998pjs.44.1681660628143; Sun, 16 Apr 2023 08:57:08 -0700 (PDT) Received: from ?IPV6:2601:681:8600:13d0::f0a? ([2601:681:8600:13d0::f0a]) by smtp.gmail.com with ESMTPSA id k2-20020a17090a3e8200b00246b5a609d2sm5714641pjc.27.2023.04.16.08.57.07 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 16 Apr 2023 08:57:07 -0700 (PDT) Message-ID: <9a3d9170-40de-597a-250b-6bec3445c4db@ventanamicro.com> Date: Sun, 16 Apr 2023 09:57:06 -0600 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.9.1 Content-Language: en-US To: "gcc-patches@gcc.gnu.org" From: Jeff Law Subject: [committed] [PR target/109508] Adjust conditional move expansion for SFB X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Recently the conditional move expander's predicates were loosened for the benefit of the THEAD processors. In particular one operand that was previously "register_operand" is now "reg_or_0_operand". That's fine for THEAD, but breaks for SFB which requires a register for that operand. This results in an ICE when compiling the testcase an SFB target such as the sifive s76. This change adjusts the expansion code slightly to copy the value into a register for SFB. Bootstrapped and regression tested (c,c++,fortran only) with a toolchain configured to enable SFB by default. Installing on the trunk momentarily. Jeff commit a647198fcf7463a42c8e035a429200e7998735dc Author: Jeff Law Date: Sun Apr 16 09:55:32 2023 -0600 [committed] [PR target/109508] Adjust conditional move expansion for SFB Recently the conditional move expander's predicates were loosened for the benefit of the THEAD processors. In particular one operand that was previously "register_operand" is now "reg_or_0_operand". That's fine for THEAD, but breaks for SFB which requires a register for that operand. This results in an ICE when compiling the testcase an SFB target such as the sifive s76. This change adjusts the expansion code slightly to copy the value into a register for SFB. Bootstrapped and regression tested (c,c++,fortran only) with a toolchain configured to enable SFB by default. PR target/109508 gcc/ * config/riscv/riscv.cc (riscv_expand_conditional_move): For TARGET_SFB_ALU, force the true arm into a register. gcc/testsuite * gcc.target/riscv/pr109508.c: New test. diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index dc47434fac4..e88fa2d6337 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -3419,6 +3419,12 @@ riscv_expand_conditional_move (rtx dest, rtx op, rtx cons, rtx alt) { riscv_emit_int_compare (&code, &op0, &op1); rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1); + + /* The expander allows (const_int 0) for CONS for the benefit of + TARGET_XTHEADCONDMOV, but that case isn't supported for + TARGET_SFB_ALU. So force that operand into a register if + necessary. */ + cons = force_reg (GET_MODE (dest), cons); emit_insn (gen_rtx_SET (dest, gen_rtx_IF_THEN_ELSE (GET_MODE (dest), cond, cons, alt))); return true; diff --git a/gcc/testsuite/gcc.target/riscv/pr109508.c b/gcc/testsuite/gcc.target/riscv/pr109508.c new file mode 100644 index 00000000000..65f291e17ed --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr109508.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-mcpu=sifive-s76" } */ + +typedef char __attribute__((__vector_size__ (1))) V; + +V v; + +void +foo (void) +{ + (char) __builtin_shuffle (0 % v, (V){6}, v); +}