From patchwork Fri Jan 10 16:48:40 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Zhijin Zeng X-Patchwork-Id: 104502 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 913803857C63 for ; Fri, 10 Jan 2025 16:50:56 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 913803857C63 Authentication-Results: sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=spacemit.com header.i=@spacemit.com header.a=rsa-sha256 header.s=feishu2303021642 header.b=D6zbW3ID X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from lf-2-38.ptr.blmpb.com (lf-2-38.ptr.blmpb.com [101.36.218.38]) by sourceware.org (Postfix) with ESMTPS id 262EA3858C48 for ; Fri, 10 Jan 2025 16:48:49 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 262EA3858C48 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=spacemit.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=spacemit.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 262EA3858C48 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=101.36.218.38 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1736527731; cv=none; b=w2eFB9+3Nvleu+wB3OB6qQPh4ptPLrH94NlPRBO9/1l6MUMX4WcLGMfAPhTtKHz7WtL3NxZScWCbYAUFKwMpwYVUpQGuCmzf8AoRHig0Huhrp8t9rW3gnqIPLCNNYVyh7mw2Oo49oqo8jlcd7Y2n8Gy7O3Z7jpwPZXbJOnpTMXE= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1736527731; c=relaxed/simple; bh=keg+J1jYDNBFn9BUME776pAEHQEYrf0aZz65ayW9uIw=; h=DKIM-Signature:Date:Message-Id:Subject:From:Mime-Version:To; b=saJh4n78PXW+pGDFxDWTVmdw9UE/U5H2D5k+GsKaCY/mRKI5IF/Ym78X9Ye3l58RrY0ycKNHI4+gIHNGAUAK4KxOgk+fe/L3wI+WdxtJZoa/xDFi8GF2SLrLBKZ6r+PMMfCtA3uFItZopXR6X1dMb7osaflMVh/9OLnH4mdXU08= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 262EA3858C48 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=feishu2303021642; d=spacemit.com; t=1736527723; h=from:subject: mime-version:from:date:message-id:subject:to:cc:reply-to:content-type: mime-version:in-reply-to:message-id; bh=keg+J1jYDNBFn9BUME776pAEHQEYrf0aZz65ayW9uIw=; b=D6zbW3IDbk8finOsLDtJAVnr9K6xnj8aCQcBTbCnoJB5cApf9+/saTYG2Dk8w9IzzGozxB lMH6K2C3i6VAurQ7Lfu7vElQnAAqcnrvPHqFAsDvn1JJO6uqYz/55vWcqIRhvF/pLVhdx6 1OjEDjoSg1Bm+p860ax+uCu2N5bd1cMwE44KymLVcU1E9qYbvK+uQ0JzA/hb7uaFQ3dUoT wlF/2EZb+ROW0p5+vN0qBG/NoPQd3CIFqR8QbT2sslcTH1zmoNZbJmMXFiU0tqSe9x0eq/ yASJSt8ldU61qSHMzbMJrQUlxfEs+SYK6QtquVV60f6yTSRAmuhj79gN9BG0YQ== Date: Sat, 11 Jan 2025 00:48:40 +0800 Message-Id: <8fd4328940034d8778cca67eaad54e5a2c2b1a6c.fcd608b5.af7d.410c.935b.211e61191843@feishu.cn> Subject: [PATCH] RISC-V: Fix riscv_modes_tieable_p From: "Zhijin Zeng" Mime-Version: 1.0 To: "gcc-patches" , "Kito Cheng" , "richard.sandiford@linaro.org" X-Lms-Return-Path: X-Spam-Status: No, score=-7.3 required=5.0 tests=BAYES_50, BODY_8BITS, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, LIKELY_SPAM_BODY, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org Integer values and floating-point values need to be converted by fmv series instructions. So if mode1 is MODE_INT and mode2 is MODE_FLOAT, we should return false in riscv_modes_tieable_p, and vice versa. gcc/ChangeLog:         * config/riscv/riscv.cc (riscv_modes_tieable_p): gcc/testsuite/ChangeLog:         * gcc.target/riscv/fwprop1-modes-tieable.c: New test. ---  gcc/config/riscv/riscv.cc                     |  5 ++  .../gcc.target/riscv/fwprop1-modes-tieable.c  | 80 +++++++++++++++++++  2 files changed, 85 insertions(+)  create mode 100644 gcc/testsuite/gcc.target/riscv/fwprop1-modes-tieable.c -- 2.25.1 This message and any attachment are confidential and may be privileged or otherwise protected from disclosure. If you are not an intended recipient of this message, please delete it and any attachment from your system and notify the sender immediately by reply e-mail. Unintended recipients should not use, copy, disclose or take any action based on this message or any information contained in this message. Emails cannot be guaranteed to be secure or error free as they can be intercepted, amended, lost or destroyed, and you should take full responsibility for security checking. 本邮件及其任何附件具有保密性质，并可能受其他保护或不允许被披露给第三方。如阁下误收到本邮件，敬请立即以回复电子邮件的方式通知发件人，并将本邮件及其任何附件从阁下系统中予以删除。如阁下并非本邮件写明之收件人，敬请切勿使用、复制、披露本邮件或其任何内容，亦请切勿依本邮件或其任何内容而采取任何行动。电子邮件无法保证是一种安全和不会出现任何差错的通信方式，可能会被拦截、修改、丢失或损坏，收件人需自行负责做好安全检查。 diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 65e09842fde..58b3b8c726c 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -9753,6 +9753,11 @@ riscv_modes_tieable_p (machine_mode mode1, machine_mode mode2)       E.g. V2SI and DI are not tieable.  */    if (riscv_v_ext_mode_p (mode1) != riscv_v_ext_mode_p (mode2))      return false; +  if ((GET_MODE_CLASS (mode1) == MODE_FLOAT +       && GET_MODE_CLASS (mode2) == MODE_INT) +       || (GET_MODE_CLASS (mode2) == MODE_FLOAT +       && GET_MODE_CLASS (mode1) == MODE_INT)) +    return false;    return (mode1 == mode2           || !(GET_MODE_CLASS (mode1) == MODE_FLOAT                && GET_MODE_CLASS (mode2) == MODE_FLOAT)); diff --git a/gcc/testsuite/gcc.target/riscv/fwprop1-modes-tieable.c b/gcc/testsuite/gcc.target/riscv/fwprop1-modes-tieable.c new file mode 100644 index 00000000000..05d775c31d2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/fwprop1-modes-tieable.c @@ -0,0 +1,80 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-rtl-fwprop1" } */ +/* { dg-skip-if "" { *-*-* } {"-Os" "-O1" "-O0" "-Og" "-Oz" "-flto"} } */ +/* { dg-final { scan-rtl-dump-not "\\(and:DI^(\s|\n)?$\\(subreg:DI^(\s|\n)?$\\(reg/v:DF" "fwprop1" } } */ + +#include + +#define EXP_TABLE_BITS 7 +#define EXP_POLY_ORDER 5 +#define EXP2_POLY_ORDER 5 +struct exp_data +{ +  double invln2N; +  double shift; +  double negln2hiN; +  double negln2loN; +  double poly[4]; /* Last four coefficients.  */ +  double exp2_shift; +  double exp2_poly[EXP2_POLY_ORDER]; +  uint64_t tab[2*(1 << EXP_TABLE_BITS)]; +}; + +extern struct exp_data __exp_data; + +#define N (1 << EXP_TABLE_BITS) +#define InvLn2N __exp_data.invln2N +#define NegLn2hiN __exp_data.negln2hiN +#define NegLn2loN __exp_data.negln2loN +#define Shift __exp_data.shift +#define T __exp_data.tab +#define C2 __exp_data.poly[5 - EXP_POLY_ORDER] +#define C3 __exp_data.poly[6 - EXP_POLY_ORDER] +#define C4 __exp_data.poly[7 - EXP_POLY_ORDER] +#define C5 __exp_data.poly[8 - EXP_POLY_ORDER] + +static inline uint64_t +asuint64 (double f) +{ +  union +  { +    double f; +    uint64_t i; +  } u = {f}; +  return u.i; +} + +static inline double +asdouble (uint64_t i) +{ +  union +  { +    uint64_t i; +    double f; +  } u = {i}; +  return u.f; +} + +double +__testexp (double x) +{ +  uint64_t ki, idx, sbits; +  double kd, z, r, scale, tmp; + +  z = InvLn2N * x; + +  kd = z + Shift; +  ki = asuint64 (kd); +  kd -= Shift; + +  r = kd * NegLn2hiN + kd * NegLn2loN; + +  idx = (ki % N); + +  sbits = T[idx]; + +  tmp = (r * C3); + +  scale = asdouble (sbits); +  return scale * tmp; +}