From patchwork Fri Apr 22 19:27:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Segher Boessenkool X-Patchwork-Id: 53136 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 35938385627B for ; Fri, 22 Apr 2022 19:28:30 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from gcc1-power7.osuosl.org (gcc1-power7.osuosl.org [140.211.15.137]) by sourceware.org (Postfix) with ESMTP id 2245C3858427 for ; Fri, 22 Apr 2022 19:27:37 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 2245C3858427 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=kernel.crashing.org Authentication-Results: sourceware.org; spf=none smtp.mailfrom=gcc1-power7.osuosl.org Received: by gcc1-power7.osuosl.org (Postfix, from userid 10019) id 547C312404E3; Fri, 22 Apr 2022 19:27:36 +0000 (UTC) From: Segher Boessenkool To: gcc-patches@gcc.gnu.org Subject: [PATCH] rs6000: Fix pack for soft-float (PR105334) Date: Fri, 22 Apr 2022 19:27:34 +0000 Message-Id: <760aa16e7ffbed4d6d12c79edc5b111e21210ba3.1650655581.git.segher@kernel.crashing.org> X-Mailer: git-send-email 1.8.3.1 X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Segher Boessenkool , dje.gcc@gmail.com, "Kewen.Lin" Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" For PR103623 I fixed unpack, but pack is broken as well, as reported in PR105334. Fixing that is a bit more code, but it is pretty simple code nonetheless. Committing to trunk. Segher 2022-04-22 Segher Boessenkool PR target/105334 * config/rs6000/rs6000.md (pack for FMOVE128): New expander. (pack for FMOVE128): Rename and split the insn_and_split to... (pack_hard for FMOVE128): ... this... (pack_soft for FMOVE128): ... and this. --- gcc/config/rs6000/rs6000.md | 45 +++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 43 insertions(+), 2 deletions(-) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index a39b95f7dffa..64049a6e521c 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -14602,13 +14602,26 @@ (define_insn_and_split "unpack_nodm" } [(set_attr "type" "fp,fpstore,store")]) -(define_insn_and_split "pack" +(define_expand "pack" + [(use (match_operand:FMOVE128 0 "register_operand")) + (use (match_operand: 1 "register_operand")) + (use (match_operand: 2 "register_operand"))] + "FLOAT128_2REG_P (mode)" +{ + if (TARGET_HARD_FLOAT) + emit_insn (gen_pack_hard (operands[0], operands[1], operands[2])); + else + emit_insn (gen_pack_soft (operands[0], operands[1], operands[2])); + DONE; +}) + +(define_insn_and_split "pack_hard" [(set (match_operand:FMOVE128 0 "register_operand" "=&d") (unspec:FMOVE128 [(match_operand: 1 "register_operand" "d") (match_operand: 2 "register_operand" "d")] UNSPEC_PACK_128BIT))] - "FLOAT128_2REG_P (mode)" + "FLOAT128_2REG_P (mode) && TARGET_HARD_FLOAT" "#" "&& reload_completed" [(set (match_dup 3) (match_dup 1)) @@ -14626,6 +14639,34 @@ (define_insn_and_split "pack" [(set_attr "type" "fp") (set_attr "length" "8")]) +(define_insn_and_split "pack_soft" + [(set (match_operand:FMOVE128 0 "register_operand" "=&r") + (unspec:FMOVE128 + [(match_operand: 1 "register_operand" "r") + (match_operand: 2 "register_operand" "r")] + UNSPEC_PACK_128BIT))] + "FLOAT128_2REG_P (mode) && TARGET_SOFT_FLOAT" + "#" + "&& reload_completed" + [(set (match_dup 3) (match_dup 1)) + (set (match_dup 4) (match_dup 2))] +{ + unsigned dest_hi = REGNO (operands[0]); + unsigned dest_lo = dest_hi + (TARGET_POWERPC64 ? 1 : 2); + + gcc_assert (!IN_RANGE (REGNO (operands[1]), dest_hi, dest_lo)); + gcc_assert (!IN_RANGE (REGNO (operands[2]), dest_hi, dest_lo)); + + operands[3] = gen_rtx_REG (mode, dest_hi); + operands[4] = gen_rtx_REG (mode, dest_lo); +} + [(set_attr "type" "integer") + (set (attr "length") + (if_then_else + (match_test "TARGET_POWERPC64") + (const_string "8") + (const_string "16")))]) + (define_insn "unpack" [(set (match_operand:DI 0 "register_operand" "=wa,wa") (unspec:DI [(match_operand:FMOVE128_VSX 1 "register_operand" "0,wa")