From patchwork Thu May 26 07:17:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chung-Ju Wu X-Patchwork-Id: 54396 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id BCB743834E43 for ; Thu, 26 May 2022 07:17:34 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org BCB743834E43 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1653549454; bh=fpvEy6d1ILodPk3ZPRIiJRGXsyRucS5IdQAGYnFrQ40=; h=Date:Subject:To:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:Cc:From; b=H3cFN3GVEn5uK5FcYagbyA3v03db0DTSVSJoWmzh7ic9Ur7vnDwGFz+gc5OWoRjYt bJWI6Ze5a8u72vGqNdktCKXh6YvdPnZNzArowckbCNLAQ8aY+UrWkJUFGww2tKXqSf J4Gg/q/OwPdOrV+2j68mKOYLlLDFNYHQA3IFkdLY= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pg1-x52e.google.com (mail-pg1-x52e.google.com [IPv6:2607:f8b0:4864:20::52e]) by sourceware.org (Postfix) with ESMTPS id 8743D3858C2C for ; Thu, 26 May 2022 07:17:04 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 8743D3858C2C Received: by mail-pg1-x52e.google.com with SMTP id e66so653261pgc.8 for ; Thu, 26 May 2022 00:17:04 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:message-id:date:mime-version:user-agent :content-language:from:subject:to:cc; bh=fpvEy6d1ILodPk3ZPRIiJRGXsyRucS5IdQAGYnFrQ40=; b=J/BjoQtfvjbCU4RD26ZoMZ/QxWVwHb4b+J3Uow4npFDtxzdnE/5ZnfO2U4Rr/elVEE 0x8ZW1U+J8FlObojDHU4dYuAbVApwHLFeHw/BMkYXq4Jb6NtU9DDqg3JvvFvNNTK4Lr5 w11K62sg0i51iM11AmZl0AML++miY34+IOxCI2MZaWCIxwJixSC8EouNlJUhxR5yiJKj w/GeQOBHR1TLRqSCBK21W1HO/SEfo4aM5Zr16GXzg/bp8Wect0v08MGaPApdnZg0uyQu BbEOTWF3GtJjeHY97xznw6XkoR/orfdFMxn+2vj5w7U4HrS9wbSsiZ/V8mOiz24jDVXS bEgg== X-Gm-Message-State: AOAM531RU9WrfjXB199Sd0t4iKnCZmWPea48LeOjX3PYxZJZvJ8HShLz SgZfW2SmIkG5oX3BzHmw3Js= X-Google-Smtp-Source: ABdhPJxTZ/awFY0DtJsdjirPlTowGNY7JBCKqIcXFnDV6w5vDziSl4Z5asTyhcwv6MC0gKfnxSBOfg== X-Received: by 2002:a05:6a00:1893:b0:518:9945:b288 with SMTP id x19-20020a056a00189300b005189945b288mr20513034pfh.75.1653549423098; Thu, 26 May 2022 00:17:03 -0700 (PDT) Received: from [10.223.1.10] (114-43-72-38.dynamic-ip.hinet.net. [114.43.72.38]) by smtp.gmail.com with ESMTPSA id g12-20020a63110c000000b003c66480613esm739352pgl.80.2022.05.26.00.17.01 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 26 May 2022 00:17:02 -0700 (PDT) Message-ID: <70e4f5ae-e59a-d0ba-68b9-72d27de09c44@gmail.com> Date: Thu, 26 May 2022 15:17:32 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.9.1 Content-Language: en-US Subject: [PATCH 1/3][ARM] STAR-MC1 CPU Support - arm: Add star-mc1 core To: Richard.Earnshaw@arm.com, gcc-patches X-Spam-Status: No, score=-10.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_SHORT, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Chung-Ju Wu via Gcc-patches From: Chung-Ju Wu Reply-To: Chung-Ju Wu Cc: Jason.Wu@anshingtek.com.tw Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Hi, STAR-MC1 is an embedded processor with armv8m architecture. Majorly it is designed to meet the requirements of AIoT application performance, power consumption and security. Early this month, star-mc1 is supported by the latest releases of MDK and CMSIS. For the completeness of Arm ecosystem, it would be great if we can have star-mc1 support in official GCC as well. Attached is the patch to support star-mc1 cpu in GCC: * Fundamental of -mcpu=star-mc1 option - Based on latest upstream commit: https://gcc.gnu.org/g:3dff965cae6709a5fd1b7b05c51c3c8aba786961 - Add star-mc1 cpu in arm-cpus.in and regenerate necessary implementation * Include VLLDM bugfix - CVE-2021-35465 also affects star-mc1 configuration [1] - We apply quirk_vlldm strategy for star-mc1 cpu Successfully bootstrapped and tested on arm-none-eabi. Is it OK for trunk? [1] https://www.cve.org/CVERecord?id=CVE-2021-35465 Regards, jasonwucj From 3405d35f4a6a6abd7808e2c62ce2d1dbd2e2cb14 Mon Sep 17 00:00:00 2001 From: Chung-Ju Wu Date: Thu, 26 May 2022 02:58:16 +0000 Subject: [PATCH 1/3] arm: Add star-mc1 core Signed-off-by: Chung-Ju Wu gcc/ChangeLog: * config/arm/arm-cpus.in: Add star-mc1 core. * config/arm/arm-tables.opt: Regenerate. * config/arm/arm-tune.md: Regenerate. --- gcc/config/arm/arm-cpus.in | 10 ++++++++++ gcc/config/arm/arm-tables.opt | 3 +++ gcc/config/arm/arm-tune.md | 4 ++-- 3 files changed, 15 insertions(+), 2 deletions(-) diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in index 0d3082b569f..5a63bc548e5 100644 --- a/gcc/config/arm/arm-cpus.in +++ b/gcc/config/arm/arm-cpus.in @@ -1638,6 +1638,16 @@ begin cpu cortex-m55 vendor 41 end cpu cortex-m55 +begin cpu star-mc1 + cname starmc1 + tune flags LDSCHED + architecture armv8-m.main+dsp+fp + option nofp remove ALL_FP + option nodsp remove armv7em + isa quirk_no_asmcpu quirk_vlldm + costs v7m +end cpu star-mc1 + # V8 R-profile implementations. begin cpu cortex-r52 cname cortexr52 diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt index ef0cc5ef0c8..e6461abcc57 100644 --- a/gcc/config/arm/arm-tables.opt +++ b/gcc/config/arm/arm-tables.opt @@ -282,6 +282,9 @@ Enum(processor_type) String(cortex-m35p) Value( TARGET_CPU_cortexm35p) EnumValue Enum(processor_type) String(cortex-m55) Value( TARGET_CPU_cortexm55) +EnumValue +Enum(processor_type) String(star-mc1) Value( TARGET_CPU_starmc1) + EnumValue Enum(processor_type) String(cortex-r52) Value( TARGET_CPU_cortexr52) diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md index 34225536042..abc290edd09 100644 --- a/gcc/config/arm/arm-tune.md +++ b/gcc/config/arm/arm-tune.md @@ -49,6 +49,6 @@ cortexa710,cortexx1,neoversen1, cortexa75cortexa55,cortexa76cortexa55,neoversev1, neoversen2,cortexm23,cortexm33, - cortexm35p,cortexm55,cortexr52, - cortexr52plus" + cortexm35p,cortexm55,starmc1, + cortexr52,cortexr52plus" (const (symbol_ref "((enum attr_tune) arm_tune)")))