From patchwork Wed Jul 13 18:18:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: will schmidt X-Patchwork-Id: 56044 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id E3BC7384D155 for ; Wed, 13 Jul 2022 18:19:06 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org E3BC7384D155 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1657736346; bh=qmVxRQADvYRSg3HBJNwtIErOTpgMNwn5Cyowlh4h4Zc=; h=Subject:To:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:Cc:From; b=mdcvNzRfIeE9EAcHBnXOAcEinOo778I0z/jp1RTz8A22yfhG03GKr8SMGIOLcjHy7 75xHPUiNck6EuINP1llx1i05S69soieku2ioNNxKcj+3BUXvEzZOLJNss0kupzU2Pe MRb5rIzC8yT3jDeftjiIkbu/r+UKOe9VLepWZZKs= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by sourceware.org (Postfix) with ESMTPS id 57939384D18D for ; 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Wed, 13 Jul 2022 18:18:31 GMT Received: from b01cxnp22036.gho.pok.ibm.com (b01cxnp22036.gho.pok.ibm.com [9.57.198.26]) by ppma02dal.us.ibm.com with ESMTP id 3h9am4sgc4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 13 Jul 2022 18:18:31 +0000 Received: from b01ledav001.gho.pok.ibm.com (b01ledav001.gho.pok.ibm.com [9.57.199.106]) by b01cxnp22036.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 26DIIU4418481990 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 13 Jul 2022 18:18:30 GMT Received: from b01ledav001.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id BF14A28059; Wed, 13 Jul 2022 18:18:30 +0000 (GMT) Received: from b01ledav001.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 58F6A28058; Wed, 13 Jul 2022 18:18:30 +0000 (GMT) Received: from lexx (unknown [9.160.8.243]) by b01ledav001.gho.pok.ibm.com (Postfix) with ESMTP; Wed, 13 Jul 2022 18:18:30 +0000 (GMT) Message-ID: <6da1e35def9d282bcf87483e78cf578fff604723.camel@vnet.ibm.com> Subject: [PATCH, rs6000] Cleanup some vstrir define_expand naming inconsistencies To: GCC Patches Date: Wed, 13 Jul 2022 13:18:29 -0500 X-Mailer: Evolution 3.28.5 (3.28.5-18.el8) Mime-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: mw8N9DaI1eLnaP2o_cOkmfFfldDYXDpY X-Proofpoint-ORIG-GUID: R3_Ps0-3Yqiiz4pDKVUmtj6Wm1YYkhmT X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-07-13_07,2022-07-13_03,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 lowpriorityscore=0 priorityscore=1501 malwarescore=0 mlxscore=0 mlxlogscore=738 impostorscore=0 spamscore=0 clxscore=1015 suspectscore=0 bulkscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2206140000 definitions=main-2207130073 X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: will schmidt via Gcc-patches From: will schmidt Reply-To: will schmidt Cc: David Edelsohn , Segher Boessenkool Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" [PATCH, rs6000] Cleanup some vstrir define_expand naming inconsistencies Hi, This cleans up some of the naming around the vstrir and vstril instruction definitions, with some cosmetic changes for consistency. No functional changes. Regtested just in case, no regressions. :-) OK for trunk? Thanks, gcc/ * config/rs6000/altivec.md (vstrir_code_): Rename to vstrir_internal_. (vstrir_p_code_): Rename to vstrir_p_internal_. (vstril_code_): Rename to vstril_internal_. (vstril_p_code_): Rename to vstril_p_internal_. diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index efc8ae35c2e7..5aea02e9ad6e 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -884,44 +884,44 @@ (define_expand "vstrir_" (unspec:VIshort [(match_operand:VIshort 1 "altivec_register_operand")] UNSPEC_VSTRIR))] "TARGET_POWER10" { if (BYTES_BIG_ENDIAN) - emit_insn (gen_vstrir_code_ (operands[0], operands[1])); + emit_insn (gen_vstrir_internal_ (operands[0], operands[1])); else - emit_insn (gen_vstril_code_ (operands[0], operands[1])); + emit_insn (gen_vstril_internal_ (operands[0], operands[1])); DONE; }) -(define_insn "vstrir_code_" +(define_insn "vstrir_internal_" [(set (match_operand:VIshort 0 "altivec_register_operand" "=v") (unspec:VIshort [(match_operand:VIshort 1 "altivec_register_operand" "v")] UNSPEC_VSTRIR))] "TARGET_POWER10" "vstrir %0,%1" [(set_attr "type" "vecsimple")]) -;; This expands into same code as vstrir_ followed by condition logic +;; This expands into same code as vstrir followed by condition logic ;; so that a single vstribr. or vstrihr. or vstribl. or vstrihl. instruction ;; can, for example, satisfy the needs of a vec_strir () function paired ;; with a vec_strir_p () function if both take the same incoming arguments. (define_expand "vstrir_p_" [(match_operand:SI 0 "gpc_reg_operand") (match_operand:VIshort 1 "altivec_register_operand")] "TARGET_POWER10" { rtx scratch = gen_reg_rtx (mode); if (BYTES_BIG_ENDIAN) - emit_insn (gen_vstrir_p_code_ (scratch, operands[1])); + emit_insn (gen_vstrir_p_internal_ (scratch, operands[1])); else - emit_insn (gen_vstril_p_code_ (scratch, operands[1])); + emit_insn (gen_vstril_p_internal_ (scratch, operands[1])); emit_insn (gen_cr6_test_for_zero (operands[0])); DONE; }) -(define_insn "vstrir_p_code_" +(define_insn "vstrir_p_internal_" [(set (match_operand:VIshort 0 "altivec_register_operand" "=v") (unspec:VIshort [(match_operand:VIshort 1 "altivec_register_operand" "v")] UNSPEC_VSTRIR)) (set (reg:CC CR6_REGNO) @@ -936,17 +936,17 @@ (define_expand "vstril_" (unspec:VIshort [(match_operand:VIshort 1 "altivec_register_operand")] UNSPEC_VSTRIR))] "TARGET_POWER10" { if (BYTES_BIG_ENDIAN) - emit_insn (gen_vstril_code_ (operands[0], operands[1])); + emit_insn (gen_vstril_internal_ (operands[0], operands[1])); else - emit_insn (gen_vstrir_code_ (operands[0], operands[1])); + emit_insn (gen_vstrir_internal_ (operands[0], operands[1])); DONE; }) -(define_insn "vstril_code_" +(define_insn "vstril_internal_" [(set (match_operand:VIshort 0 "altivec_register_operand" "=v") (unspec:VIshort [(match_operand:VIshort 1 "altivec_register_operand" "v")] UNSPEC_VSTRIL))] "TARGET_POWER10" @@ -962,18 +962,18 @@ (define_expand "vstril_p_" (match_operand:VIshort 1 "altivec_register_operand")] "TARGET_POWER10" { rtx scratch = gen_reg_rtx (mode); if (BYTES_BIG_ENDIAN) - emit_insn (gen_vstril_p_code_ (scratch, operands[1])); + emit_insn (gen_vstril_p_internal_ (scratch, operands[1])); else - emit_insn (gen_vstrir_p_code_ (scratch, operands[1])); + emit_insn (gen_vstrir_p_internal_ (scratch, operands[1])); emit_insn (gen_cr6_test_for_zero (operands[0])); DONE; }) -(define_insn "vstril_p_code_" +(define_insn "vstril_p_internal_" [(set (match_operand:VIshort 0 "altivec_register_operand" "=v") (unspec:VIshort [(match_operand:VIshort 1 "altivec_register_operand" "v")] UNSPEC_VSTRIL)) (set (reg:CC CR6_REGNO)